ymq.vhdl

来自「主持人按开始抢答后」· VHDL 代码 · 共 32 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ymq is
  port
    (int:in std_logic_vector(3 downto 0);
     out7:out std_logic_vector(6 downto 0));
end ymq;
architecture Behavioral of ymq is
  signal win:std_logic_vector(3 downto 0);
  signal ooo:std_logic_vector(6 downto 0);
begin
     win<=int;
   process(win)
     begin 
case win is
when "0000"=>ooo<="0000001";     --0
when "0001"=>ooo<="1001111";
when "0010"=>ooo<="0010010";
when "0011"=>ooo<="0000110";
when "0100"=>ooo<="1001100";
when "0101"=>ooo<="0100100";
when "0110"=>ooo<="0100000";
when "0111"=>ooo<="0001111";
when "1000"=>ooo<="0000000";	     --8
when "1001"=>ooo<="0000100";	     --9
when others=>ooo<="1111111";
	    end case;
   end process;
   out7<=ooo;
end Behavioral;