fpq.vhdl

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fpq is
port(clkin:in std_logic;
   clkout:out std_logic);
end fpq;
architecture Behavioral of fpq is
	    signal counter:integer range 0 to 15999999;
         signal clkaaa:std_logic;
	    
   begin
   
   process(clkin,counter)
      variable clk:std_logic:='0';
      begin
           if rising_edge(clkin) then
	            if counter=15999 then
		           counter<=0;
		           clk:=not clk;
		          else
		           counter<=counter+1;
		         end if;
	         end if;
		    clkaaa<=clk;
   end process;
   clkout<=clkaaa;
end Behavioral;