代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
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www.eeworm.com/read/168078/9940311
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity my_division is
port(
glbclk : in vl_logic;
reset : in vl_logic;
clk_1000 : out vl_log
www.eeworm.com/read/362404/10000296
qsf ps2tolcd.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
www.eeworm.com/read/361321/10058482
qsf miaobiao.qsf
# Copyright (C) 1991-2008 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
www.eeworm.com/read/360252/10105564
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
ROC_WIDTH : integer := 100000;
TOC_WIDTH : integer := 0
);
end glbl;
www.eeworm.com/read/359174/10162680
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
roc_width : integer := 100000;
toc_width : integer := 0
);
end glbl;
www.eeworm.com/read/163111/10175060
mpf i2c_slave.mpf
;
; Copyright Model Technology, a Mentor Graphics Corporation company 2003,
; All rights reserved.
;
[Library]
std = $MODEL_TECH/../std
ieee = $MODEL_TECH/../ieee
verilog = $MODEL_TECH/../ver
www.eeworm.com/read/356809/10221008
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ShiftRegController is
port(
Clock50MHz : in vl_logic;
BitStreamIn : in vl_logic;
SampleCLKfromDM : in
www.eeworm.com/read/356716/10222442
makefile
#
# PacoBlaze Makefile
#
# Path for the Xilinx sources
XILINX = ../xilinx
# Xilinx implementation of PicoBlaze
KCPSM2 = $(XILINX)/kcpsm2.v
KCPSM3 = $(XILINX)/kcpsm3.v
UNISIMS = $(wildcard
www.eeworm.com/read/162707/10280604
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity counter_4 is
port(
clk : in vl_logic;
reset : in vl_logic;
ce : in vl_logic
www.eeworm.com/read/162707/10280611
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity comparator_4 is
port(
clk : in vl_logic;
reset : in vl_logic;
a : in vl_lo