_primary.vhd

用Verilog 实现将比特流数据转化为SPI协议数据的适配器

library verilog;
use verilog.vl_types.all;
entity ShiftRegController is
    port(
        Clock50MHz      : in     vl_logic;
        BitStreamIn     : in     vl_logic;
        SampleCLKfromDM : in     vl_logic;
        SampleCLK       : out    vl_logic;
        DataOut         : out    vl_logic_vector(31 downto 0)
    );
end ShiftRegController;