_primary.vhd

来自「综合仿真程序」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity counter_4 is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        ce              : in     vl_logic;
        load            : in     vl_logic;
        dir             : in     vl_logic;
        din             : in     vl_logic_vector(15 downto 0);
        count           : out    vl_logic_vector(15 downto 0)
    );
end counter_4;