_primary.vhd

一个电子中的verilog实验源代码。适合verilog初学者学习参考

library verilog;
use verilog.vl_types.all;
entity my_division is
    port(
        glbclk          : in     vl_logic;
        reset           : in     vl_logic;
        clk_1000        : out    vl_logic;
        clk_100         : out    vl_logic;
        clk_5           : out    vl_logic;
        clk_1           : out    vl_logic
    );
end my_division;