代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
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www.eeworm.com/read/434289/7877052
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity test is
generic(
period : integer := 200;
duty_cycle : real := 0.500000;
offset : integer := 0
www.eeworm.com/read/298792/7935099
cfg compxlib.cfg
#*****************************************************************
# compxlib initialization file (compxlib.cfg) *
#
www.eeworm.com/read/297692/8004137
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity and1 is
port(
y : out vl_logic;
in1 : in vl_logic
);
end and1;
www.eeworm.com/read/297692/8004157
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_asynch_lcell is
generic(
operation_mode : string := "normal";
sum_lutc_input : string := "datac";
lut_mask
www.eeworm.com/read/397329/8055398
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity RegFile is
port(
RsData : out vl_logic_vector(31 downto 0);
RtData : out vl_logic_vector(31 downto 0);
www.eeworm.com/read/397329/8055474
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ALU is
port(
ALUResult : out vl_logic_vector(31 downto 0);
ALUcontrol : in vl_logic_vector(3 downto 0);
www.eeworm.com/read/329295/12963357
qmsg dct.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
www.eeworm.com/read/140218/13096034
qsf cpld_bus.qsf
# Copyright (C) 1991-2004 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any oth
www.eeworm.com/read/325462/13205209
rpt i2c.map.rpt
Analysis & Synthesis report for i2c
Sun Nov 18 16:17:53 2007
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Not
www.eeworm.com/read/137348/13327244
make
../../../bench/verilog/oc8051_tb.v ../../../rtl/verilog/oc8051_top.v ../../../rtl/verilog/oc8051_alu_src1_sel.v ../../../rtl/verilog/oc8051_alu_src2_sel.v ../../../rtl/verilog/oc8051_alu_src3_sel.v ..