dct.map.qmsg

8x8DCT verilog code 一次輸入8個點

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jun 12 16:42:37 2008 " "Info: Processing started: Thu Jun 12 16:42:37 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DCT -c DCT " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DCT -c DCT" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/verilog/dct/DCT/DCT_1d_12b.v " "Warning: Can't analyze file -- file D:/verilog/dct/DCT/DCT_1d_12b.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DCT_1d_8b.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file DCT_1d_8b.v" { { "Info" "ISGN_ENTITY_NAME" "1 DCT_1d_8b " "Info: Found entity 1: DCT_1d_8b" {  } { { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DCT.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file DCT.v" { { "Info" "ISGN_ENTITY_NAME" "1 DCT " "Info: Found entity 1: DCT" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "DCT " "Info: Elaborating entity \"DCT\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 DCT.v(36) " "Warning (10230): Verilog HDL assignment warning at DCT.v(36): truncated value with size 32 to match size of target (13)" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 36 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 DCT.v(37) " "Warning (10230): Verilog HDL assignment warning at DCT.v(37): truncated value with size 32 to match size of target (13)" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 37 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 DCT.v(38) " "Warning (10230): Verilog HDL assignment warning at DCT.v(38): truncated value with size 32 to match size of target (13)" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 38 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 DCT.v(39) " "Warning (10230): Verilog HDL assignment warning at DCT.v(39): truncated value with size 32 to match size of target (13)" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 39 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 DCT.v(40) " "Warning (10230): Verilog HDL assignment warning at DCT.v(40): truncated value with size 32 to match size of target (13)" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 40 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 DCT.v(41) " "Warning (10230): Verilog HDL assignment warning at DCT.v(41): truncated value with size 32 to match size of target (13)" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 41 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 DCT.v(42) " "Warning (10230): Verilog HDL assignment warning at DCT.v(42): truncated value with size 32 to match size of target (13)" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 42 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 DCT.v(43) " "Warning (10230): Verilog HDL assignment warning at DCT.v(43): truncated value with size 32 to match size of target (13)" {  } { { "DCT.v" "" { Text "D:/verilog/dct/DCT/DCT.v" 43 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "IVRFX_MULTI_DIMENSION_OBJECT_INFO" "F " "Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"F\" into its bus" {  } {  } 0 10008 "Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"%1!s!\" into its bus" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DCT_1d_8b DCT_1d_8b:DCT_1d_8b " "Info: Elaborating entity \"DCT_1d_8b\" for hierarchy \"DCT_1d_8b:DCT_1d_8b\"" {  } { { "DCT.v" "DCT_1d_8b" { Text "D:/verilog/dct/DCT/DCT.v" 33 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "show0\[9\] DCT_1d_8b.v(19) " "Warning (10034): Output port \"show0\[9\]\" at DCT_1d_8b.v(19) has no driver" {  } { { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "show0\[8\] DCT_1d_8b.v(19) " "Warning (10034): Output port \"show0\[8\]\" at DCT_1d_8b.v(19) has no driver" {  } { { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "show0\[7\] DCT_1d_8b.v(19) " "Warning (10034): Output port \"show0\[7\]\" at DCT_1d_8b.v(19) has no driver" {  } { { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "show0\[6\] DCT_1d_8b.v(19) " "Warning (10034): Output port \"show0\[6\]\" at DCT_1d_8b.v(19) has no driver" {  } { { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "show0\[5\] DCT_1d_8b.v(19) " "Warning (10034): Output port \"show0\[5\]\" at DCT_1d_8b.v(19) has no driver" {  } { { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "show0\[4\] DCT_1d_8b.v(19) " "Warning (10034): Output port \"show0\[4\]\" at DCT_1d_8b.v(19) has no driver" {  } { { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "show0\[3\] DCT_1d_8b.v(19) " "Warning (10034): Output port \"show0\[3\]\" at DCT_1d_8b.v(19) has no driver" {  } { { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "show0\[2\] DCT_1d_8b.v(19) " "Warning (10034): Output port \"show0\[2\]\" at DCT_1d_8b.v(19) has no driver" {  } { { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "show0\[1\] DCT_1d_8b.v(19) " "Warning (10034): Output port \"show0\[1\]\" at DCT_1d_8b.v(19) has no driver" {  } { { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "show0\[0\] DCT_1d_8b.v(19) " "Warning (10034): Output port \"show0\[0\]\" at DCT_1d_8b.v(19) has no driver" {  } { { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "show1\[9\] DCT_1d_8b.v(19) " "Warning (10034): Output port \"show1\[9\]\" at DCT_1d_8b.v(19) has no driver" {  } { { "DCT_1d_8b.v" "" { Text "D:/verilog/dct/DCT/DCT_1d_8b.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}