_primary.vhd

来自「用VHDL设计具有简单MIPS功能的源码」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity RegFile is
    port(
        RsData          : out    vl_logic_vector(31 downto 0);
        RtData          : out    vl_logic_vector(31 downto 0);
        clk             : in     vl_logic;
        RegWriteData    : in     vl_logic_vector(31 downto 0);
        RegWriteAddr    : in     vl_logic_vector(4 downto 0);
        RegWriteEn      : in     vl_logic;
        RsAddr          : in     vl_logic_vector(4 downto 0);
        RtAddr          : in     vl_logic_vector(4 downto 0)
    );
end RegFile;