代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
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v hdl_demo.v
module hdl_demo(rst, clk, start_value, in_a, in_b, in_c, accum_a, accum_b, result);
input rst, clk, in_a, in_b, in_c;
input [7:0] accum_a, accum_b;
input [31:0] start_value;
output [7:0] result;
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v hdl_demo.v
module hdl_demo(rst, clk, start_value, in_a, in_b, in_c, accum_a, accum_b, result);
input rst, clk, in_a, in_b, in_c;
input [7:0] accum_a, accum_b;
input [31:0] start_value;
output [7:0] result;
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pstex hdl_uri.pstex
%!PS-Adobe-2.0 EPSF-2.0
%%Title: hdl_uri.pstex
%%Creator: fig2dev Version 3.2 Patchlevel 1
%%CreationDate: Fri May 26 03:12:07 2000
%%For: marilen@len (Marilen Corciovei)
%%Orientation: Portrait
%%Bou
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fig hdl_uri.fig
#FIG 3.2
Landscape
Center
Inches
Letter
80.00
Single
-2
1200 2
1 2 0 2 0 7 100 0 -1 6.000 1 2.4435 6637 5707 1650 975 7275 7515 6000 3900
1 2 0 2 0 7 100 0 -1 6.000 1 3.3161 5244 5324 1650 975 7039
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jpg hdl_uri.jpg
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hif part4.hif
Version 8.1 Build 163 10/28/2008 SJ Web Edition
11
1009
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
synplcty.lmf
-- Start Partition --
-- End Partition --
-- Start Li
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qmsg beep.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
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qmsg prev_cmp_beep.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
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qmsg prev_cmp_beep.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
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tcl hdlsynchk.tcl
check_hdl -file "C:/Actel_lab/LCD_1602/hdl/LCD_Top.v" -language verilog -library work -family Fusion -verbose no