hdl_uri.fig

將Verilog設計轉成VHDL設計的程式

#FIG 3.2
Landscape
Center
Inches
Letter  
80.00
Single
-2
1200 2
1 2 0 2 0 7 100 0 -1 6.000 1 2.4435 6637 5707 1650 975 7275 7515 6000 3900
1 2 0 2 0 7 100 0 -1 6.000 1 3.3161 5244 5324 1650 975 7039 5997 3450 4650
1 2 0 2 0 7 100 0 -1 6.000 1 4.0143 6517 4539 1650 975 8325 3900 4710 5175
4 0 0 100 0 2 16 0.0000 4 225 780 3975 5550 Verilog\001
4 0 0 100 0 2 16 0.0000 4 165 690 6750 6300 VHDL\001
4 0 0 100 0 2 16 0.0000 4 165 960 6600 4275 HDL-uri\001
4 0 0 100 0 2 16 0.0000 4 165 450 6525 3900 Alte\001
4 0 0 100 0 2 16 0.0000 4 120 795 5775 5400 comune\001
4 0 0 100 0 2 16 0.0000 4 165 960 5475 5100 Elemente\001