part4.hif

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

Version 8.1 Build 163 10/28/2008 SJ Web Edition
11
1009
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
synplcty.lmf
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
part4
# storage
db|part4.(0).cnf
db|part4.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
part4.v
25ae59a79f7e19694858b34bbb6342e
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
|
}
# lmf
..|..|..|..|..|..|..|altera|81|quartus|lmf|synplcty.lmf
162350f825563d4021fb6efd602a891d
# macro_sequence

# end
# entity
display
# storage
db|part4.(1).cnf
db|part4.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
part4.v
25ae59a79f7e19694858b34bbb6342e
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
display:Dis1
display:Dis2
display:Dis3
display:Dis4
}
# lmf
..|..|..|..|..|..|..|altera|81|quartus|lmf|synplcty.lmf
162350f825563d4021fb6efd602a891d
# macro_sequence

# end
# complete