代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/452281/7442781
v testbench.v
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Xilinx, Inc.
// All Rights Reserved
//////////////////////////////////////////////////////////
www.eeworm.com/read/449305/7509010
vhd testbench.vhd
library ieee;
use STD.TEXTIO.all;
use IEEE.STD_LOGIC_TEXTIO.all;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.std_logic_arith.all;
entity testbench is
end testbench;
www.eeworm.com/read/448726/7526489
scs testbench.scs
// Test circuit for quantizer
simulator lang=spectre
ahdl_include "quantizer.vams"
Vclk (clk 0) vsource type=pulse val1=1 period=1us
Vin (in 0) vsource type=sine ampl=1 freq=5kHz sinephase=45
Qua
www.eeworm.com/read/447464/7550655
v testbench.v
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Xilinx, Inc.
// All Rights Reserved
//////////////////////////////////////////////////////////
www.eeworm.com/read/442189/7657597
v testbench.v
module TestBench;
reg [10:0] Vmem [1: 0] ;
reg [2: 0] A , B;
reg Cin;
wire [2:0] Sum;
wire Cout;
reg [2: 0] Sum_Ex;
reg Cout_Ex;
reg [2
www.eeworm.com/read/434564/7859390
vhd testbench.vhd
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:50:28 04/27/2005
-- Design Name: loopback
-- Module Name: testbe
www.eeworm.com/read/297692/8004239
v testbench.v
`timescale 1 ns / 1 ps
module test_high_speed_io();
reg[1:0] rx_in;
reg rx_inclock;
reg rx_data_align;
wire rx_locked;
wire [1:0] tx_out;
wire tx_outclock;
reg data_clk;
Diff_io_top diff_io
www.eeworm.com/read/396105/8125878
vhd testbench.vhd
use std.textio.all;
library ieee;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lab10_tb is
end lab10_tb;
architecture test of lab10_tb is
component lab10 is
Port( Cl
www.eeworm.com/read/396000/8137219
pdf testbench.pdf
www.eeworm.com/read/145284/12738833
v testbench.v
`include "params.v"
`define D_PER
/************************************************************************************/
module VD();
reg CLOCK;
initial CLOCK = 0;
always #(