testbench.v

code for kcpcm3 : Describes the working of KCPCM3 embedded in picoblaze xilinx

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Xilinx, Inc.
// All Rights Reserved
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: 1.01
//  \   \         Filename: testbench.v
//  /   /         Date Last Modified:  08/04/2004
// /___/   /\     Date Created: 06/xx/2003
// \   \  /  \
//  \___\/\___\
//
//Device:  	Xilinx
//Purpose: 	
// 	Test Bench for kcpsm3_int_test.vhd
//Reference:
// 	None
//Revision History:
//    Rev 1.00 - kc - Start of design entry in VHDL,  06/xx/2003.
//    Rev 1.01 - sus - Converted to verilog,  08/04/2004.
////////////////////////////////////////////////////////////////////////////////
// Contact: e-mail  [e-mail]
//////////////////////////////////////////////////////////////////////////////////
//
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//////////////////////////////////////////////////////////////////////////////////



`timescale 1ns/100ps

module testbench;
  
// signals to connect kcpsm3_int_test 

wire [7:0] counter;
wire [7:0] waveforms;
reg interrupt_event;
reg clk;

// Define the unit under test

   kcpsm3_int_test uut
   (         .counter(counter),
             .waveforms(waveforms),
             .interrupt_event(interrupt_event),
             .clk(clk) );


// Test Bench begins
 
  // Nominal 50MHz clock which also defines number of cycles in simulation 


   parameter PERIOD = 20;

   always begin
      clk = 1'b0;
      #(PERIOD/2) clk = 1'b1;
      #(PERIOD/2);
   end  

initial
	begin
		interrupt_event <= 1'b0; 
      	#(30*PERIOD) interrupt_event <= 1'b1; 
		#(PERIOD) interrupt_event <= 1'b0; 
		#(67*PERIOD) interrupt_event <= 1'b1;
		#(PERIOD) interrupt_event <= 1'b0;  
		#(30*PERIOD) interrupt_event <= 1'b1; 
		#(PERIOD) interrupt_event <= 1'b0; 
		#(20*PERIOD);
    end

endmodule