testbench.v

来自「一位全加器」· Verilog 代码 · 共 28 行

module    TestBench;
reg    [10:0]    Vmem   [1: 0] ;
 reg     [2: 0]      A , B;
  reg     Cin;
wire        [2:0] Sum;
 wire        Cout;

 reg     [2: 0]   Sum_Ex;
 reg              Cout_Ex;
 reg [2:0]   counter;

//被测试验证的模块实例。
Adder3Bit    F1  (A, B, Cin, Sum, Cout ) ;
initial
  begin
        $readmemb ("test.vec", Vmem );
         for (counter=0; counter<=1; counter = counter+ 1)
         begin
              {A, B, Cin, Sum_Ex, Cout_Ex}= Vmem [counter] ;
                  #5; //延迟5个时间单位等待电路稳定。
       if ( (Sum!=Sum_Ex) || (Cout!=Cout_Ex) )
        $display ("****Mismatch on vector: %b *****", Vmem[counter] ) ;
       else
          $display ("No mismatch on vector :%b", Vmem[counter] ) ;
        end
end
endmodule