testbench.vhd

VHDL：用状态机的方法实现一个8位乘法器

use std.textio.all;
library ieee;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity lab10_tb is
end lab10_tb;

architecture test of lab10_tb is
    component lab10 is
    Port( Clock        : in std_logic;
          Reset        : in std_logic;
          Multiplier   : in std_logic_vector(7 downto 0);
          Multiplicand : in std_logic_vector(7 downto 0);
          LoadData     : in std_logic;
          ProductOut   : out std_logic_vector(15 downto 0);
          ProductDone  : out std_logic);
    end component;
    
    signal clock        : std_logic;
    signal reset        : std_logic;
    signal Multiplier   : std_logic_vector(7 downto 0);
    signal Multiplicand : std_logic_vector(7 downto 0);
    signal LoadData     : std_logic;
    signal ProductOut   : std_logic_vector(15 downto 0);
    signal ProductDone  : std_logic;

    procedure multiply_two (
        constant multiplier_in   : in  std_logic_vector(7 downto 0);
        constant multiplicand_in : in  std_logic_vector(7 downto 0);
        constant answer          : in  std_logic_vector(15 downto 0);
        signal   LdData          : out std_logic;
        signal   Multiplier      : out std_logic_vector(7 downto 0);
        signal   Multiplicand    : out std_logic_vector(7 downto 0)
    ) is
    variable L : line;
    begin
        wait until clock = '1' and clock'event;
        -- Load the multiplier and multiplicand into their respective registers
        Multiplier   <= multiplier_in;
        Multiplicand <= multiplicand_in;
        LdData       <= '1';
        wait until clock = '1' and clock'event;
        LdData       <= '0';
        -- Wait until Multiplication finished
        wait until ProductDone = '1' and clock = '1' and clock'event;
        if ProductOut = answer then
            write (L, 'c');
        else
            write (L, 'i');
        end if;
        writeline (output, L);
        wait until ProductDone = '0';
    end multiply_two;

begin  -- testbench

    uut : lab10 port map (
        Clock        => clock,
        Reset        => reset,
        Multiplier   => multiplier,
        Multiplicand => multiplicand,
        LoadData     => LoadData,
        ProductOut   => ProductOut,
        ProductDone  => ProductDone);

    clock_gen : process
    begin  -- process clock_gen
        clock <= '0';
        wait for 10 ns;
        clock <= '1';
        wait for 10 ns;
    end process clock_gen;
    
    test_mult8 : process
    begin  -- process test_mult8
        LoadData    <= '0';
        Multiplicand <= (others => '0');
        Multiplier   <= (others => '0');
        reset        <= '0';
        wait for 30 ns;
        reset        <= '1';
        multiply_two("00000100", "00000010", "0000000000001000", LoadData, Multiplicand, Multiplier);
        multiply_two("00001010", "00000101", "0000000000110010", LoadData, Multiplicand, Multiplier);
        multiply_two("00000000", "01010101", "0000000000000000", LoadData, Multiplicand, Multiplier);
        multiply_two("00101010", "00000000", "0000000000000000", LoadData, Multiplicand, Multiplier);
        multiply_two("01111111", "01111111", "0011111100000001", LoadData, Multiplicand, Multiplier);
        multiply_two("11111100", "11111110", "1111101000001000", LoadData, Multiplicand, Multiplier);
        multiply_two("11110110", "11111011", "1111000100110010", LoadData, Multiplicand, Multiplier);
        multiply_two("00000000", "11010101", "0000000000000000", LoadData, Multiplicand, Multiplier);
        multiply_two("10101010", "00000000", "0000000000000000", LoadData, Multiplicand, Multiplier);
        multiply_two("00000100", "11111110", "0000001111111000", LoadData, Multiplicand, Multiplier);
        multiply_two("00001010", "11111011", "0000100111001110", LoadData, Multiplicand, Multiplier);
        multiply_two("11111110", "00000100", "0000001111111000", LoadData, Multiplicand, Multiplier);
        multiply_two("11111011", "00001010", "0000100111001110", LoadData, Multiplicand, Multiplier);
        --    report "TEST BENCH COMPLETED" severity WARNING;
        report "COMPLETION" severity WARNING;
        wait;
    end process test_mult8;

end test;