代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/449295/7509159
do fifo_tb_runtest.do
SetActiveLib -work
comp "$DSN\src\rm16x16.bde"
comp "$DSN\src\rm16x32.bde"
comp "$DSN\src\c4ud.bde"
comp "$DSN\src\c4u.bde"
comp "$DSN\src\fifod.bde"
comp "$DSN\src\fd16d.bde"
comp "$DSN\
www.eeworm.com/read/196650/8069011
vht ctl_1.vht
-- VHDL Test Bench Created from source file ctl_1.vhd -- Tue Apr 18 19:24:36 2006
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_lo
www.eeworm.com/read/329969/12922949
transcript
# Reading D:/ispTOOLS7_0/modelsim/tcl/vsim/pref.tcl
# do getpcm_t.fdo
# ** Warning: (vlib-34) Library already exists at "work".
# getpcmdata.sty
# pcm.vhd uartrec.vhd baudr.vhd uartsend.vhd getp
www.eeworm.com/read/109657/6173165
do compile_and_run_timing_fullmodel.do
##
# Verilog Build requirements for Timing simulation of the Full Stripe Model
# Device = epxa10
vlib work
vlog "$env(MG_MODEL_PATH)/epxa10/$env(MG_MODEL_REV)/mti_modelsim_verilog/apex20ke_str
www.eeworm.com/read/109657/6173171
do compile_and_run_timing_fullmodel.do
##
# Verilog Build requirements for Timing simulation of the Full Stripe Model
# Device = epxa10
vlib work
vlog "$env(MG_MODEL_PATH)/epxa10/$env(MG_MODEL_REV)/mti_modelsim_verilog/apex20ke_str
www.eeworm.com/read/217282/14970883
_deps
H 2141964 10 3 0 2 2 0 0 0 0
L 4 ieee 19 $MODEL_TECH/../ieee
L 3 std 18 $MODEL_TECH/../std
L 4 work 4 work
D 30 work.delay_tbw(testbench_arch) GEFAHLhMDEW7:`0DzJK3 1 1
D 26 work.delay_vhd(behavioral
www.eeworm.com/read/217282/14970902
_deps
H 2141964 10 3 0 2 2 0 0 0 0
L 4 ieee 19 $MODEL_TECH/../ieee
L 3 std 18 $MODEL_TECH/../std
L 4 work 4 work
D 31 work.delay_tbw1(testbench_arch) BN^j:?6[J4^8kMV6me8HM1 1 1
D 26 work.delay_vhd(behaviora
www.eeworm.com/read/217282/14970923
_deps
H 2141964 10 3 0 2 2 0 0 0 0
L 4 ieee 19 $MODEL_TECH/../ieee
L 3 std 18 $MODEL_TECH/../std
L 4 work 4 work
D 31 work.delay_tbw3(testbench_arch) aGKn`o44XK``zz87jWlP01 1 1
D 26 work.delay_vhd(behaviora
www.eeworm.com/read/217282/14970963
ref hdllib.ref
AR delay_tbw1 testbench_arch C:/Xilinx/LIUXJ/DELAY1/DELAY_tbw1.vhw sub00/vhpl05 1178456186
EN delay_tbw NULL C:/Xilinx/LIUXJ/DELAY1/DELAY_tbw.ant sub00/vhpl02 1178456116
EN delay_vhd NULL D:/MY_DESI
www.eeworm.com/read/217279/14971285
_deps
H 2141964 10 3 0 2 2 0 0 0 0
L 4 ieee 19 $MODEL_TECH/../ieee
L 3 std 18 $MODEL_TECH/../std
L 4 work 4 work
D 23 work.ccdout(behavioral) enZ5n4@U4oYD;nD>O_8c:3 0 1
D 31 work.ccdout_tbw(testbench_arch)