ctl_1.vht

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-- VHDL Test Bench Created from source file ctl_1.vhd -- Tue Apr 18 19:24:36 2006
--
-- Notes: 
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Lattice recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "source->import"
-- menu in the ispDesignExpert System Project Navigator to import the testbench.
-- Then edit the user defined section below, adding code to generate the 
-- stimulus for your design.
--
LIBRARY ieee;
LIBRARY generics;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE generics.components.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS 

	COMPONENT ctl_1
	PORT(
		W4 : IN std_logic;
		W3 : IN std_logic;
		W2 : IN std_logic;
		W1 : IN std_logic;
		T1 : IN std_logic;
		SWC : IN std_logic;
		SWB : IN std_logic;
		SWA : IN std_logic;
		MF : IN std_logic;
		IR7 : IN std_logic;
		IR6 : IN std_logic;
		IR5 : IN std_logic;
		IR4 : IN std_logic;
		CLR : IN std_logic;
		C : IN std_logic;          
		WRD : OUT std_logic;
		TJ : OUT std_logic;
		SW_BUS : OUT std_logic;
		SKIP : OUT std_logic;
		S2 : OUT std_logic;
		S1 : OUT std_logic;
		S0 : OUT std_logic;
		RS_BUS : OUT std_logic;
		PC_ADD : OUT std_logic;
		M4 : OUT std_logic;
		M3 : OUT std_logic;
		LRW : OUT std_logic;
		LDPC : OUT std_logic;
		LDIR : OUT std_logic;
		LDER : OUT std_logic;
		LDDR1 : OUT std_logic;
		LDAR1 : OUT std_logic;
		CEL : OUT std_logic;
		AR1_INC : OUT std_logic;
		ALU_BUS : OUT std_logic
		);
	END COMPONENT;

	SIGNAL WRD :  std_logic;
	SIGNAL W4 :  std_logic;
	SIGNAL W3 :  std_logic;
	SIGNAL W2 :  std_logic;
	SIGNAL W1 :  std_logic;
	SIGNAL TJ :  std_logic;
	SIGNAL T1 :  std_logic;
	SIGNAL SW_BUS :  std_logic;
	SIGNAL SWC :  std_logic;
	SIGNAL SWB :  std_logic;
	SIGNAL SWA :  std_logic;
	SIGNAL SKIP :  std_logic;
	SIGNAL S2 :  std_logic;
	SIGNAL S1 :  std_logic;
	SIGNAL S0 :  std_logic;
	SIGNAL RS_BUS :  std_logic;
	SIGNAL PC_ADD :  std_logic;
	SIGNAL MF :  std_logic;
	SIGNAL M4 :  std_logic;
	SIGNAL M3 :  std_logic;
	SIGNAL LRW :  std_logic;
	SIGNAL LDPC :  std_logic;
	SIGNAL LDIR :  std_logic;
	SIGNAL LDER :  std_logic;
	SIGNAL LDDR1 :  std_logic;
	SIGNAL LDAR1 :  std_logic;
	SIGNAL IR7 :  std_logic;
	SIGNAL IR6 :  std_logic;
	SIGNAL IR5 :  std_logic;
	SIGNAL IR4 :  std_logic;
	SIGNAL CLR :  std_logic;
	SIGNAL CEL :  std_logic;
	SIGNAL C :  std_logic;
	SIGNAL AR1_INC :  std_logic;
	SIGNAL ALU_BUS :  std_logic;

BEGIN

	uut: ctl_1 PORT MAP(
		WRD => WRD,
		W4 => W4,
		W3 => W3,
		W2 => W2,
		W1 => W1,
		TJ => TJ,
		T1 => T1,
		SW_BUS => SW_BUS,
		SWC => SWC,
		SWB => SWB,
		SWA => SWA,
		SKIP => SKIP,
		S2 => S2,
		S1 => S1,
		S0 => S0,
		RS_BUS => RS_BUS,
		PC_ADD => PC_ADD,
		MF => MF,
		M4 => M4,
		M3 => M3,
		LRW => LRW,
		LDPC => LDPC,
		LDIR => LDIR,
		LDER => LDER,
		LDDR1 => LDDR1,
		LDAR1 => LDAR1,
		IR7 => IR7,
		IR6 => IR6,
		IR5 => IR5,
		IR4 => IR4,
		CLR => CLR,
		CEL => CEL,
		C => C,
		AR1_INC => AR1_INC,
		ALU_BUS => ALU_BUS
	);


-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN
      wait; -- will wait forever
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;