fifo_tb_runtest.do

FIFo参考设计16x32 FIFO with simultaneous read/write operations.

SetActiveLib -work
comp "$DSN\src\rm16x16.bde" 
comp "$DSN\src\rm16x32.bde" 
comp "$DSN\src\c4ud.bde" 
comp "$DSN\src\c4u.bde" 
comp "$DSN\src\fifod.bde" 
comp "$DSN\src\fd16d.bde" 
comp "$DSN\src\fifo.bde" 
acom "$DSN\src\TB_vhd\fifo_TB.vhd" 
asim -advdataflow TESTBENCH_FOR_fifo 
wave 
wave -noreg DIP
wave -noreg DOP
wave -noreg CLKP
wave -noreg EMPTYP
wave -noreg FULLP
wave -noreg LASTP
wave -noreg POPP
wave -noreg PUSHP
run 1820.00 ns
# The following lines can be used for timing simulation
# acom <backannotated_vhdl_file_name>
# comp "$DSN\src\TB_vhd\fifo_TB_tim_cfg.vhd" 
# asim TIMING_FOR_fifo