transcript

PCM数据采集

# Reading D:/ispTOOLS7_0/modelsim/tcl/vsim/pref.tcl 
# do getpcm_t.fdo 
# ** Warning: (vlib-34) Library already exists at "work".
# getpcmdata.sty
# pcm.vhd uartrec.vhd baudr.vhd uartsend.vhd getpcm.vhd
# Model Technology ModelSim LATTICE vcom 6.2g Compiler 2007.02 Feb 22 2007
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity pcm
# -- Compiling architecture art_pcm of pcm
# Model Technology ModelSim LATTICE vcom 6.2g Compiler 2007.02 Feb 22 2007
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity uartrec
# -- Compiling architecture atr_uartrec of uartrec
# Model Technology ModelSim LATTICE vcom 6.2g Compiler 2007.02 Feb 22 2007
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity baudr
# -- Compiling architecture art_baudr of baudr
# Model Technology ModelSim LATTICE vcom 6.2g Compiler 2007.02 Feb 22 2007
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity uartsend
# -- Compiling architecture art_uartsend of uartsend
# Model Technology ModelSim LATTICE vcom 6.2g Compiler 2007.02 Feb 22 2007
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity getpcm
# -- Compiling architecture art_getpcm of getpcm
# getpcm_t.vhd
# Model Technology ModelSim LATTICE vcom 6.2g Compiler 2007.02 Feb 22 2007
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling entity testbench
# -- Compiling architecture behavior of testbench
# vsim -L pmi_work testbench 
# //  ModelSim LATTICE 6.2g Feb 22 2007 
# //
# //  Copyright 1991-2007 Mentor Graphics Corporation
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading D:\ispTOOLS7_0\modelsim\win32loem/../std.standard
# Loading D:\ispTOOLS7_0\modelsim\win32loem/../ieee.std_logic_1164(body)
# Loading D:\ispTOOLS7_0\modelsim\win32loem/../ieee.numeric_std(body)
# Loading work.testbench(behavior)
# Loading D:\ispTOOLS7_0\modelsim\win32loem/../ieee.std_logic_arith(body)
# Loading D:\ispTOOLS7_0\modelsim\win32loem/../ieee.std_logic_unsigned(body)
# Loading work.getpcm(art_getpcm)
# Loading work.uartsend(art_uartsend)
# Loading work.baudr(art_baudr)
# Loading work.uartrec(atr_uartrec)
# Loading work.pcm(art_pcm)
# vsim -L pmi_work testbench 
# Loading D:\ispTOOLS7_0\modelsim\win32loem/../std.standard
# Loading D:\ispTOOLS7_0\modelsim\win32loem/../ieee.std_logic_1164(body)
# Loading D:\ispTOOLS7_0\modelsim\win32loem/../ieee.numeric_std(body)
# Loading work.testbench(behavior)
# Loading D:\ispTOOLS7_0\modelsim\win32loem/../ieee.std_logic_arith(body)
# Loading D:\ispTOOLS7_0\modelsim\win32loem/../ieee.std_logic_unsigned(body)
# Loading work.getpcm(art_getpcm)
# Loading work.uartsend(art_uartsend)
# Loading work.baudr(art_baudr)
# Loading work.uartrec(atr_uartrec)
# Loading work.pcm(art_pcm)
add wave sim:/testbench/uut/wrclock
add wave sim:/testbench/uut/uartbusy
restart
run
restart
run
write format wave -window .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf D:/CPLD/GetPcmSim/wave.do