代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/112957/6142625
vhd testdes.vhd
-- VHDL Test Bench Created from source file encrypt.vhd -- 02:44:54 01/24/2003
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the p
www.eeworm.com/read/347395/11668123
do sim.do
#退出上一次仿真
quit -sim
#建立work库
vlib work
#把ModelSim所要使用的work库映射到新建立的work库上
vmap work work
#编译Altera的仿真库文件
vlog altera_mf.v
#编译设计文件
vlog DualPortRAM.v
#编译顶层文件
vlog TOP.v
#编译testben
www.eeworm.com/read/347395/11668133
do sim.do
#退出上一次仿真
quit -sim
#建立work库
vlib work
#把ModelSim所要使用的work库映射到新建立的work库上
vmap work work
#编译Altera的仿真库文件
vlog altera_mf.v
#编译设计文件
vlog DualPortRAM.v
#编译顶层文件
vlog TOP.v
#编译testben
www.eeworm.com/read/471689/6888133
do run.do
quietly set ACTELLIBNAME proasic3
quietly set PROJECT_DIR "C:/Documents and Settings/BySky/My Documents/4bitcomp"
if {[file exists presynth/_info]} {
puts "INFO: Simulation library presynth al
www.eeworm.com/read/32644/1035349
pdf 第三部分8：testbench.pdf
www.eeworm.com/read/40249/1138621
pdf 第三部分8：testbench.pdf
www.eeworm.com/read/431805/8654034
v fpadd_32tb.v
// Adder Testbench
`timescale 1ns/10ps
module testbed();
integer i;
reg add_sub;
reg [31:0] fp_a, fp_b;
wire [31:0] fp_z;
FPadd_24 A1(add_sub, fp_a, fp_b, fp_z);
initial
begin
www.eeworm.com/read/387422/8684771
npl canbus.npl
JDF G
// Created by Project Navigator ver 1.0
PROJECT canbus
DESIGN canbus
DEVFAM spartan2e
DEVFAMTIME 0
DEVICE xc2s300e
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
D
www.eeworm.com/read/167222/9975039
v test_register.v
module testbench_register;
wire [7:0] register_out,register_in;
wire clk,reset,load_enable;
test t (register_out,register_in,clk,reset,load_enable);
register r (register_out,regi
www.eeworm.com/read/281220/10255870
do test_func.do
-- (c) Copyright 2003 Xilinx, Inc
-- All rights reserved
vlib work
vmap work work
vcom -reportprogress 300 -work work StrataFlash3V.vhd
vcom -reportprogress 300 -work work cis.vhd
vcom -report