test_func.do

CF VHDL The CF+ design was designed using the timing diagrams of the Compact Flash specification re

-- (c) Copyright 2003 Xilinx, Inc
-- All rights reserved

vlib work
vmap work work
vcom -reportprogress 300 -work work StrataFlash3V.vhd
vcom -reportprogress 300 -work work cis.vhd
vcom -reportprogress 300 -work work attribute_memory.vhd
vcom -reportprogress 300 -work work cf_plus_control.vhd
vcom -reportprogress 300 -work work upcnt6.vhd
vcom -reportprogress 300 -work work dsp_interface.vhd
vcom -reportprogress 300 -work work cf_plus.vhd
vcom -reportprogress 300 -work work testbench.vhd
vsim work.testbench
view wave
do wave_func.do
view structure
view signals

run 4 ms