fpadd_32tb.v

来自「一个32位元的浮点数加法器」· Verilog 代码 · 共 27 行

// Adder Testbench
`timescale 1ns/10ps
module testbed();
  integer i;
  reg add_sub;
  reg [31:0] fp_a, fp_b;
  wire [31:0] fp_z;

  FPadd_24 A1(add_sub, fp_a, fp_b, fp_z);

initial
begin 
    for(i = 0; i < 5000; i = i + 1)
    begin
      #50 add_sub = {$random} % 2; fp_a = {$random} %4294967296 ; fp_b = {$random} % 4294967296;
    end
    $stop;
end

initial
  begin
    $dumpfile("flp_adder_32.vcd");
    $dumpvars;
end

endmodule