test_register.v

来自「本代码是在modelsim下运行的模拟8×8位的CPU」· Verilog 代码 · 共 38 行

module testbench_register;
   wire [7:0] register_out,register_in;
   wire clk,reset,load_enable;
   
   test t (register_out,register_in,clk,reset,load_enable);
   register  r (register_out,register_in,clk,reset,load_enable);
   
endmodule 
   
module test(register_out,register_in,clk,reset,load_enable);
   parameter width = 8;

   input[width-1:0] register_out;  //??????
   output [width-1:0] register_in; //??????
   output clk;                     //????????????
   output reset;                   //????????????
   output load_enable;             //??????

   reg   [width-1:0] register_in;
   reg   clk,reset,load_enable;
   
   initial begin
      $monitor($time,,,"register_out=%b,register_in=%b,clk=%b,reset=%b,load_enable=%b",register_out,register_in,clk,reset,load_enable ); 
         #5  reset=0;
         #5  clk=0;register_in=8'b00010001;
         #5  clk=1;
         #5  reset=1;
         #5  clk=0;
         #5  clk=1;load_enable=1;
         #5  clk=0;
         #5  clk=0;load_enable=1;register_in=8'b11010001;
         #5  clk=0;register_in=8'b11111111;load_enable=0;
         #5  clk=1;load_enable=1;
         #5  reset=0;
    end
endmodule