代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/376214/2712012
testbench
#
# This file is part of Minimalist OpenGL Environment (MinGLE)
#
# Version: 0.2.0
# Author: Balazs Domonkos
# Filename: samples/bin/testbench
# Creation Date: January 30th 2008
# Revision Date
www.eeworm.com/read/412328/11204448
testbench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity divclk1_tb is
end divclk1_tb;
architecture behavior of divclk1_tb is
component divclk1
port(clk: in std_logic;
divclk:
www.eeworm.com/read/188244/8555370
v testbench.v
`timescale 1ns/1ns
module testbench;
reg clk;
reg rst;
reg codein;
wire [1:0] codeoutv;
wire [1:0] codeoutb;
initial
begin
clk
www.eeworm.com/read/187975/8583132
v testbench.v
`timescale 1ns/1ps
module testbench;
wire [7:0] data_bus,address_out,data_in;
wire RW;
reg clk;
reg reset;
CPU b (.data_out(data_bus),.address_out,.CS,.READ,.WRITE,.clk,.
www.eeworm.com/read/430376/8753050
v testbench.v
`timescale 1ns/1ns
`include "ahbdec.v"
`include "ahbarb.v"
`include "ahbmst.v"
`include "ahbslv.v"
`include "demo_amba_for_tb.v"
module t;
`include "ahb_def.v"
reg hclk;
reg
www.eeworm.com/read/286093/8788630
fdo testbench.fdo
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Wed Jun 20 18:35:51 中国标准时间 2007
##
vlib work
vcom -93 -explicit qdq.vhdl
vcom -93 -explicit ymq.vhdl
vcom -93 -ex
www.eeworm.com/read/286093/8788758
udo testbench.udo
-- ProjNav VHDL simulation template: testbench.udo
-- You may edit this file after the line that starts with
-- '-- START' to customize your simulation
-- START user-defined simulation commands
www.eeworm.com/read/384797/8843304
vhd testbench.vhd
-- AccelDSP 9.1.00 build 868 Production, compiled Feb 16 2007
--
-- THIS IS UNPUBLISHED, LICENSED SOFTWARE THAT IS THE CONFIDENTIAL
-- AND PROPRIETARY PROPERTY OF XILINX OR ITS L
www.eeworm.com/read/185211/9050283
vhd testbench_a.vhd
entity TEST_BENCH is
end TEST_BENCH;
use work.all;
architecture AUTOCOR1 of TEST_BENCH is
signal B: BIT_VECTOR(3 downto 0);
signal A: BIT_VECTOR(2 downto 0);
SIGNAL RUN:BIT;
SIGNAL
www.eeworm.com/read/185211/9050306
vhd testbench.vhd
entity TEST_BENCH is
end TEST_BENCH;
use work.all;
architecture AUTOCOR1 of TEST_BENCH is
SIGNAL DIN: BIT_VECTOR(3 downto 0);
SIGNAL A: BIT_VECTOR(2 downto 0);
SIGNAL RUN:BIT;
SIGNA