testbench.vhd

浮点fir设计工具

--       AccelDSP 9.1.00 build 868 Production, compiled Feb 16 2007 
-- 
--    THIS IS UNPUBLISHED, LICENSED SOFTWARE THAT IS THE CONFIDENTIAL 
--        AND PROPRIETARY PROPERTY OF XILINX OR ITS LICENSORS 
-- 
--      Copyright(c) Xilinx, Inc., 2000-2007, All Rights Reserved. 
--   Reproduction or reuse, in any form, without the explicit written 
--          consent of Xilinx, Inc., is strictly prohibited. 
-- 
--  User: WangQian 
--  Machine: A2D3DF917F70473 (i1586, Windows XP Service Pack 2, 5.01.2600) 
--  Date: Mon May 12 10:57:37 2008 
-- 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.accel_tb_utils.all;


entity testbench is
		generic(

			max_errors 		 : integer := 0;
			clock_period 		 : time := 10.000 ns;
			clock_high 		 : time := 5.000 ns;
			clock_low 		 : time := 5.000 ns;
			fixed 		 : integer := 1;
			delayed 		 : integer := 0;
			random_min 		 : integer := 0;
			random_max 		 : integer := 0;
			reset_offset 		 : time := 100 ns;
			input_delay_type 		 : integer := 0;
			input_delay_amount 		 : integer := 0;
			output_delay_type 		 : integer := 0;
			output_delay_amount 		 : integer := 0;
			push_mode_delay 		 : integer := 16;
			dut_sample_rate 		 : integer := 16;
			dut_latency 		 : integer := 16
		);
end testbench;

architecture RTL of testbench is

		component fir
		port (
			indatabuf : in signed( 11 downto 0 );
			outdatabuf : out signed( 25 downto 0 );
			ac_InputAvail : in std_logic;
			ac_OutputAvail : out std_logic;
			Clock : in std_logic;
			Reset : in std_logic
		);
		end component;

		signal tb_indatabuf : signed( 11 downto 0 );
		signal indatabuf : signed( 11 downto 0 );
		signal tb_outdatabuf : signed( 25 downto 0 );
		signal tb_outdatabufEOF : std_logic;
		signal tb_outdatabufErrors : integer := 0;
		signal outdatabuf : signed( 25 downto 0 );
		signal Clock : std_logic;
		signal Reset : std_logic;
		signal min : integer;
		signal max : integer;
		signal iteration : integer;
		signal complete : std_logic;
		signal errors : integer := 0;
		signal DUTClock : std_logic;
		signal ac_InputAvail : std_logic;
		signal tb_ac_InputAvail : std_logic;
		signal ac_OutputAvail : std_logic;
		signal tb_ac_OutputAvail : std_logic;
begin

		DUTClock <= ( not Clock );

		dut:
			fir
			port map (
				indatabuf => indatabuf,
				outdatabuf => outdatabuf,
				ac_InputAvail => ac_InputAvail,
				ac_OutputAvail => ac_OutputAvail,
				Clock => DUTClock,
				Reset => Reset
			);

			errors <= tb_outdatabufErrors ;
			complete <= tb_outdatabufEOF ;

			simulation:
				accel_monitor
				generic map (
					max_errors => max_errors,
					clock_period => clock_period,
					clock_high => clock_high,
					clock_low => clock_low,
					fixed => fixed,
					delayed => delayed,
					random_min => random_min,
					random_max => random_max,
					reset_offset => reset_offset,
					input_delay_type => input_delay_type,
					input_delay_amount => input_delay_amount,
					output_delay_type => output_delay_type,
					output_delay_amount => output_delay_amount,
					push_mode_delay => push_mode_delay,
					dut_sample_rate => dut_sample_rate,
					dut_latency => dut_latency
				)
				port map (
					reset => Reset,
					clock => Clock,
					errors => errors,
					eos => complete,
					min => min,
					max => max,
					iteration => iteration
				);

				ac_InputAvail <= tb_ac_InputAvail;
		indatabuf <= tb_indatabuf(11 downto 0);
		tb_indatabufComponent:
				input_generator_signed
				generic map (
					filename => "Accel_TestVector_indatabuf.txt",
					precision => 4,
					resolution => 8,
					num_of_elements => 1,
					input_delay_type => input_delay_type,
					input_delay_amount => input_delay_amount,
					output_delay_type => output_delay_type,
					output_delay_amount => output_delay_amount,
					push_mode_delay => push_mode_delay,
					dut_sample_rate => dut_sample_rate,
					dut_latency => dut_latency
				)
				port map (
					rst => Reset,
					clk => Clock,
					data_req => '1',
					data => tb_indatabuf,
					data_avail => tb_ac_InputAvail,
					end_of_file => open
				);

				tb_ac_OutputAvail <= ac_OutputAvail;

		tb_outdatabuf(25 downto 0) <= outdatabuf;
		tb_outdatabufComponent:
				output_data_handler_signed
				generic map (
					filename_tb => "Accel_TestVector_outdatabuf_tb.txt",
					filename_fp => "Accel_TestVector_outdatabuf.txt",
					filename_compare => "ac_timing_Accel_TestVector_outdatabuf.txt",
					precision => 18,
					resolution => 8,
					num_of_elements => 1,
					ram_init_latency => 0,
					input_delay_type => input_delay_type,
					input_delay_amount => input_delay_amount,
					output_delay_type => output_delay_type,
					output_delay_amount => output_delay_amount,
					push_mode_delay => push_mode_delay,
					dut_sample_rate => dut_sample_rate,
					dut_latency => dut_latency
				)
				port map (
					rst => Reset,
					clk => Clock,
					data_avail => tb_ac_OutputAvail,
					data => tb_outdatabuf,
					data_ack => open,
					end_of_file => tb_outdatabufEOF,
					error_cnt => tb_outdatabufErrors
				);

end RTL;