testbench.vhd

The objective of this projectis to design, model and simulate an autocorrelation generator circuit

entity TEST_BENCH is
end TEST_BENCH;


use work.all;
architecture AUTOCOR1 of TEST_BENCH is

    SIGNAL DIN: BIT_VECTOR(3 downto 0);
    SIGNAL A: BIT_VECTOR(2 downto 0);
    SIGNAL RUN:BIT;
    SIGNAL RST:BIT;
    SIGNAL LOAD:BIT;
    SIGNAL CLOCK:BIT;
    
      component OSCILLATOR
      generic (HI_TIME,LO_TIME:TIME);
      port (RUN: in BIT; CLOCK: out BIT :='0');
      end component;
    
      component AUTOCORGEN 
         --generic (RDEL,CLKDEL:TIME);
         port(DIN: in BIT_VECTOR(3 downto 0);
         CLOCK: in BIT;
         RST: in BIT;
         LOAD : in BIT;
         A: out BIT_VECTOR(2 downto 0));
      end component;
    
     for L1:   OSCILLATOR use entity  COSC(ALG);
     for L2: AUTOCORGEN use entity  autoa(BEH);
     
     
     begin
     L1: OSCILLATOR
     generic map(100 ns, 100 ns)
     port map(RUN,CLOCK);
     
     L2: AUTOCORGEN
     --generic map(13 ns,10 ns)
     port map(DIN,CLOCK,RST,LOAD,A);
     
      
     
       RST <= '0',
       	      '1' after 1600 ns,
       	      '1' after 3200 ns,    
       	      '1' after 4800 ns,
       	      '1' after 6400 ns;  
       	      
       	      
       RUN <= '1','0' after 6500 ns;
          DIN <= "0000" ,         
               "0001" after 1600 ns,
               "0010" after 3200 ns,
               "0011" after 4800 ns,
               "1100" after 6400 ns;
               
          
       LOAD <=  '1','0'after 50 ns,
       		'1' after 1600 ns,'0' after 1650 ns, 
       		'1' after 3200 ns,'0' after 3250 ns,
       		'1' after 4800 ns,'0' after 4850 ns,
       		'1' after 6400 ns,'0' after 6450 ns; 
       		
     
            
       end AUTOCOR1;