inv.vhd

来自「The objective of this projectis to desig」· VHDL 代码 · 共 21 行

-- INVS model

USE WORK.ALL;
entity INV is 
    generic(constant TPLH:TIME:=2 ns;
            constant TPHL:TIME:=3 ns);
    port (I1:in BIT; O: out BIT);
end INV;

architecture BEH of INV is
begin 
P1: process(I1)
begin
   if (I1='1') then
      O<= not I1 after TPHL;
      else O<=not I1 after TPLH;
   end if;  
end process P1; 
      end BEH;