代码搜索：strobe
找到约 441 项符合「strobe」的源代码
代码结果 441
www.eeworm.com/read/340665/3268994
c test.c
extern int led_putnum();
#define DELAY 900000
extern char strobe(),putDebugChar(),print(),putnum();
extern char foobar();
extern char breakpoint();
#define TESTSTUB 1
main()
{
unsigned char x;
www.eeworm.com/read/172784/9690468
tab veriuser_vcs.tab
// Example Synopsys VCS PLI table to register PLI applications
// For the book, "The Verilog PLI Handbook"
$my_strobe data=0 check=PLIbook_MyStrobe_checktf call=PLIbook_MyStrobe_c
www.eeworm.com/read/293827/8270100
v sd_top.v
`timescale 1 ns / 100 ps
module sd_top( data_req, // sdram select
wr_l, // write strobe
sdram_en, // sdram enable
clk, // sdram clock
rs
www.eeworm.com/read/152843/5665125
h spitz.h
/*
* Hardware specific definitions for SL-Cx000 series of PDAs
*
* Copyright (c) 2005 Alexander Wykes
* Copyright (c) 2005 Richard Purdie
*
* Based on Sharp's 2.4 kernel patches
*
* This progr
www.eeworm.com/read/202490/15381523
txt printer port.txt
(编程控制示例）（为汇编代码）
// 此段代码为并口向打印机进行写数据，并发送控制信息。
#define LPT_CLEAR_MASK 0x40
#define LPT_STROBE_HI 0x0D
#define LPT_STROBE_LO 0x0C
#define LPT_STATUS_BITS 0xF8
#define LPT_BITS_INVERT 0x48
#def
www.eeworm.com/read/418184/10960248
v adc_max186_sm.v
//*****************************************************************************************//
// Project : FPGA based Digital Design using Verilog HDL
// File : adc_max186_sm.v
/
www.eeworm.com/read/258433/11864872
v mem_usr_rd.v
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// All Rights Reserved
//////////////////////////////////////////////////////////////
www.eeworm.com/read/183819/9136600
txt ddr_sdram_post_summary.txt
NOTE: Speed Grade c6 used for analysis
NOTE: Memory device can operate at 85.00 MHz with a lower CL than 2.5
DDR read data capture: DDR Data to DQS strobe edges at capture registers.
www.eeworm.com/read/354875/10317901
txt ddr_sdram_post_summary.txt
NOTE: Speed Grade c6 used for analysis
NOTE: Memory device can operate at 85.00 MHz with a lower CL than 2.5
DDR read data capture: DDR Data to DQS strobe edges at capture registers.
www.eeworm.com/read/297458/8016593
txt ddr_sdram_post_summary.txt
NOTE: Speed Grade c6 used for analysis
NOTE: Memory device can operate at 85.00 MHz with a lower CL than 2.5
DDR read data capture: DDR Data to DQS strobe edges at capture registers.