sd_top.v

8读8写SDRAM verilog 程序

`timescale 1 ns /  100 ps

module sd_top( 	data_req,         // sdram select
				wr_l,               // write strobe
				sdram_en,			// sdram enable
				clk,                // sdram clock
				rst_l,              // reset signal
				byte_en,            // byte enables
				add,                // address bus
				sd_cke,             // sdram clock enable
				sd_ba,              // sdram bank address
				sd_cs0_l,           // sdram chip select 0
				sd_ras_l,           // sdram row address
				sd_cas_l,           // sdram column select
				sd_we_l,            // sdram write enable
				sd_add,             // sdram address
				sd_dqm,             // sdram data qual mask
                sdram_setup,		// sdram setup completed

				rs_ready,
				data_cycle,
				state_cntr
				);       
				
//---------------------------------------------------------------------
// inputs
input          	data_req;
input          	wr_l;
input			sdram_en;
input          	clk;
input          	rst_l;
input  [15:0]   byte_en;
input  [24:0]  	add;
input			rs_ready;
output			data_cycle;

//---------------------------------------------------------------------
// outputs
output         	sd_cke;
output [1:0]   	sd_ba;
output         	sd_cs0_l,
               	sd_ras_l,
				sd_cas_l,
				sd_we_l;
output [11:0]  	sd_add;
output [15:0]   sd_dqm;              // change width for data width
output          sdram_setup;


output [7:0]    state_cntr;


//---------------------------------------------------------------------
// intermodule wires

//---------------------------------------------------------------------
// modules
wire	fresh_req,fresh_req_a,fresh_req_b;
assign	fresh_req=fresh_req_a | fresh_req_b;

wire	load_req;
wire	charge_req;
wire	data_req;
	
wire	idle_cycle;
wire	load_cycle;
wire	data_cycle;
wire	fresh_cycle;
wire	charge_cycle;
//wire[7:0]	state_cntr;


 sd_cnfg	u1(	.sdram_en(sdram_en),
				.clk(clk),
               	.rst_l(rst_l),

               	.load_req(load_req),
				.charge_req(charge_req),
				.fresh_req(fresh_req_a),

				.load_cycle(load_cycle),
				.fresh_cycle(fresh_cycle),
				.charge_cycle(charge_cycle),
               	.sdram_setup(sdram_setup)
			);

sd_state u2(
               	.clk(clk),
               	.rst_l(rst_l),

                .fresh_req(fresh_req),
                .load_req(load_req),
				.charge_req(charge_req),
				.data_req(data_req),	
					
				.idle_cycle(idle_cycle),		
				.load_cycle(load_cycle),	
				.data_cycle(data_cycle), 		
				.fresh_cycle(fresh_cycle), 		
				.charge_cycle(charge_cycle),
				.state_cntr(state_cntr)
			);
			
sd_rfrsh u3(  		
               	.clk(clk),
               	.rst_l(rst_l),
				.fresh_cycle(fresh_cycle), 
                .fresh_req(fresh_req_b)
				);

sd_sig u4(  
               	.rst_l(rst_l),                 
               	.clk(clk),

				.add(add),
               	.wr_l(wr_l),
               	.byte_en(byte_en),

				.idle_cycle(idle_cycle),		
				.load_cycle(load_cycle),	
				.data_cycle(data_cycle), 		
				.fresh_cycle(fresh_cycle), 		
				.charge_cycle(charge_cycle),
				
				.state_cntr(state_cntr),

               	.sd_add(sd_add),
               	.sd_ba(sd_ba),
               	.sd_cs0_l(sd_cs0_l),
               	.sd_ras_l(sd_ras_l),
               	.sd_cas_l(sd_cas_l),
               	.sd_we_l(sd_we_l),
               	.sd_cke(sd_cke),
               	.sd_dqm(sd_dqm),

				.rs_ready(rs_ready)
				);
endmodule