adc_max186_sm.v

it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in x

//*****************************************************************************************//
//    Project      : FPGA based Digital Design using Verilog HDL
//    File         : adc_max186_sm.v
//    Author       : Irfan Faisal Mir & Nauman Mir
//    Company      : Chip Designing Course
//    Start Date   : 
//    Last Updated : 
//    Version      : 0.1
//    Abstract     : This module implements...........
// 
//    Modification History:
//==========================================================================================
//    Date                       By                    Version            Change Description
//==========================================================================================
//                               Irfan & Nauman        0.1                Original Version
//
//******************************************************************************************//
                         
// ADC Controller (State Machine)
module adc_max186_sm(// Inputs
                         clk_1MHz,
                         rst_n,
                         ai_enb_sig,
                         adc_strobe_p,
                         cnt_bits,
                         wach_dog_cnt,
                         // Outputs
                         sel_ch_sig,
                         adc_cs_sig,
                         ld_data_sig,
                         tx_data_sig,
                         wait_strobe_sig,
                         rx_data_sig,
                         rxdata_valid_sig,
                         adc_scan_comp_sig
                        );
//======= Port Declaration =========//
input        clk_1MHz ;
input        rst_n ;
input        ai_enb_sig ;
input        adc_strobe_p ;
input [3:0]  cnt_bits ;
input [2:0]  wach_dog_cnt ;

output       sel_ch_sig ;
output       adc_cs_sig ;
output       ld_data_sig ;
output       tx_data_sig ;
output       wait_strobe_sig ;
output       rx_data_sig ;
output       rxdata_valid_sig ;
output       adc_scan_comp_sig ;

// One-Hot State Encoding..
parameter [6:0] IDLE           = 7'b1000000 ;
parameter [6:0] SELECT_CH      = 7'b0100000 ;
parameter [6:0] LD_CONTRL_DATA = 7'b0010000 ;
parameter [6:0] TX_CONTRL_DATA = 7'b0001000 ;
parameter [6:0] WAIT_STROBE    = 7'b0000100 ;
parameter [6:0] RX_DATA        = 7'b0000010 ;
parameter [6:0] SCAN_COMP      = 7'b0000001 ;               

reg [6:0] adc_state ;

reg       adc_cs_sig ;
reg       ld_data_sig ;
reg       tx_data_sig ;
reg       wait_strobe_sig ;
reg       rx_data_sig ;
reg       rxdata_valid_sig ;
reg       sel_ch_sig ;
reg       adc_scan_comp_sig ;


                                 
always @(posedge clk_1MHz or negedge rst_n)
begin
   if(~rst_n) begin
      adc_state <= #1 IDLE ;
   end
   else begin
      case(adc_state)
         IDLE : begin
                   if(ai_enb_sig)
                      adc_state <= #1 SELECT_CH ;
                   else
                      adc_state <= #1 IDLE ;
                end
         SELECT_CH : begin
                        adc_state <= #1 LD_CONTRL_DATA ;
                     end
         LD_CONTRL_DATA : begin  // Load Control Byte Data
                              adc_state <= #1 TX_CONTRL_DATA ;
                           end
         TX_CONTRL_DATA : begin  // Shift Control Byte
                              if(cnt_bits == 4'd7)
                                 adc_state <= #1 WAIT_STROBE ;
                              else
                                 adc_state <= #1 TX_CONTRL_DATA ;
                           end
         WAIT_STROBE : begin  // Wait for Strobe signal from ADC chip
                              if(wach_dog_cnt == 3'd7)
                                 adc_state <= #1 IDLE ;
                              else if(adc_strobe_p)
                                 adc_state <= #1 RX_DATA ;
                              else
                                 adc_state <= #1 WAIT_STROBE ;
                           end
         RX_DATA : begin // Data Rx from ADC chip
                      if(cnt_bits == 4'd14)
                         adc_state <= #1 SCAN_COMP ;
                      else
                         adc_state <= #1 RX_DATA ;
                   end
         SCAN_COMP : begin   // Scan has been completed here
                            adc_state <= #1 IDLE ;
                         end
         default : begin
                      adc_state <= #1 IDLE ;
                   end
      endcase                                                 
   end
end                                 

always @(adc_state)
begin
   case(adc_state)
      IDLE : begin
                adc_cs_sig = 1'b1 ;
                ld_data_sig = 1'b0 ;
                tx_data_sig = 1'b0 ;
                wait_strobe_sig = 1'b0 ;
                rx_data_sig = 1'b0 ;
                rxdata_valid_sig = 1'b0 ;
                sel_ch_sig = 1'd0 ;
                adc_scan_comp_sig = 1'b0 ;
             end
      SELECT_CH : begin
                     adc_cs_sig = 1'b0 ;
                     ld_data_sig = 1'b0 ;
                     tx_data_sig = 1'b0 ;
                     wait_strobe_sig = 1'b0 ;
                     rx_data_sig = 1'b0 ;
                     rxdata_valid_sig = 1'b0 ;
                     sel_ch_sig = 1'b1 ;
                     adc_scan_comp_sig = 1'b0 ;
                  end
      LD_CONTRL_DATA : begin  // Load Control Byte Data
                           adc_cs_sig = 1'b0 ;
                           ld_data_sig = 1'b1 ;
                           tx_data_sig = 1'b0 ;
                           wait_strobe_sig = 1'b0 ;
                           rx_data_sig = 1'b0 ;
                           rxdata_valid_sig = 1'b0 ;
                           sel_ch_sig = 1'b0 ;
                           adc_scan_comp_sig = 1'b0 ;
                        end
      TX_CONTRL_DATA : begin  // Shift Control Byte
                           adc_cs_sig = 1'b0 ;
                           ld_data_sig = 1'b0 ;
                           tx_data_sig = 1'b1 ;
                           wait_strobe_sig = 1'b0 ;
                           rx_data_sig = 1'b0 ;
                           rxdata_valid_sig = 1'b0 ;
                           sel_ch_sig = 1'b0 ;
                           adc_scan_comp_sig = 1'b0 ;
                        end
      WAIT_STROBE : begin  // Wait for Strobe signal from ADC chip
                           adc_cs_sig = 1'b0 ;
                           ld_data_sig = 1'b0 ;
                           tx_data_sig = 1'b0 ;
                           wait_strobe_sig = 1'b1 ;
                           rx_data_sig = 1'b0 ;
                           rxdata_valid_sig = 1'b0 ;
                           sel_ch_sig = 1'd0 ;
                           adc_scan_comp_sig = 1'b0 ;
                        end
      RX_DATA : begin // Data Rx from ADC chip
                   adc_cs_sig = 1'b0 ;
                   ld_data_sig = 1'b0 ;
                   tx_data_sig = 1'b0 ;
                   wait_strobe_sig = 1'b0 ;
                   rx_data_sig = 1'b1 ;
                   rxdata_valid_sig = 1'b0 ;
                   sel_ch_sig = 1'd0 ;
                   adc_scan_comp_sig = 1'b0 ;
                end
      SCAN_COMP : begin   // Scan has been completed here
                         adc_cs_sig = 1'b1 ;
                         ld_data_sig = 1'b0 ;
                         tx_data_sig = 1'b0 ;
                         wait_strobe_sig = 1'b0 ;
                         rx_data_sig = 1'b0 ;
                         rxdata_valid_sig = 1'b1 ;
                         sel_ch_sig = 1'd0 ;
                         adc_scan_comp_sig = 1'b0 ;
                      end
      default : begin
                   adc_cs_sig = 1'b1 ;
                   ld_data_sig = 1'b0 ;
                   tx_data_sig = 1'b0 ;
                   wait_strobe_sig = 1'b0 ;
                   rx_data_sig = 1'b0 ;
                   rxdata_valid_sig = 1'b0 ;
                   sel_ch_sig = 1'd0 ;
                end
   endcase                                                 
end                                 

endmodule