mem_usr_rd.v

xilinx公司的ＤＤＲ实现源码

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: 1.0
//  \   \         Filename: addr_gen.v
//  /   /         Timestamp: 12 Dec 2005
// /___/   /\     
// \   \  /  \
//  \___\/\___\
//
//
//Device: Virtex-5
///////////////////////////////////////////////////////////////////////////////

                 
module mem_usr_rd (
  input                            CLK,
  input                            RESET,
  input [`data_width-1:0]          READ_DATA_RISE,
  input [`data_width-1:0]          READ_DATA_FALL,
  input [`data_strobe_width-1:0]   CTRL_RDEN,
  output                    READ_DATA_VALID,
  output [`data_width-1:0]  READ_DATA_FIFO_RISE, 
  output [`data_width-1:0]  READ_DATA_FIFO_FALL

                     );



 wire [`data_strobe_width-1:0]  READ_EN_DELAYED_RISE;
 wire [`data_strobe_width-1:0]  READ_EN_DELAYED_FALL;

 reg fifo_read_enable_r;
 reg fifo_read_enable_2r;
 

  wire  [`data_strobe_width-1:0] rd_data_valid;



assign READ_DATA_VALID = rd_data_valid[0];




   always @ (posedge CLK)
   begin
     if (RESET == 1'b1)
       begin
         fifo_read_enable_r   <= 1'b0;
         fifo_read_enable_2r   <= 1'b0;


       end
     else
       begin
         fifo_read_enable_r   <= CTRL_RDEN[0];
         fifo_read_enable_2r   <= fifo_read_enable_r;
         
       end
   end



genvar fifo_i;
generate
   for(fifo_i= 0; fifo_i < `data_strobe_width; fifo_i = fifo_i+1)
     begin:fifo_inst
           
       mem_usr_rd_fifo rd_data_fifo
		(
                      .CLK		            (CLK),
                      .RESET	            (RESET),
                      .FIFO_RD_EN           (fifo_read_enable_2r),
		      .READ_EN_DELAYED_RISE (CTRL_RDEN[fifo_i]),
		      .READ_EN_DELAYED_FALL (CTRL_RDEN[fifo_i]),
                      .READ_DATA_RISE       (READ_DATA_RISE[((fifo_i*8)+7):fifo_i*8]),
                      .READ_DATA_FALL       (READ_DATA_FALL[((fifo_i*8)+7):fifo_i*8]),
                      .READ_DATA_FIFO_RISE  (READ_DATA_FIFO_RISE[((fifo_i*8)+7):fifo_i*8]),
                      .READ_DATA_FIFO_FALL  (READ_DATA_FIFO_FALL[((fifo_i*8)+7):fifo_i*8]),
                      .READ_DATA_VALID      (rd_data_valid[fifo_i])
                     );   

     end // block: dq_inst
   endgenerate






   endmodule