代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/137595/13310556
vhd buff8.vhd
library ieee;
use ieee.std_logic_1164.all;
entity buff8 is
port(a,b : inout std_logic_vector(7 downto 0);
ncs,rd,wr : in std_logic);
end buff8;
architecture buff8_arch of buff8 is
si
www.eeworm.com/read/137517/13318017
txt 计数器：generate语句的应用.txt
-- Generated Binary Up Counter
-- The first design entity is a T-type flip-flop.
-- The second is an scalable synchronous binary up counter illustrating the use of the generate statement to produce
www.eeworm.com/read/137515/13318045
txt 计数器：generate语句的应用.txt
-- Generated Binary Up Counter
-- The first design entity is a T-type flip-flop.
-- The second is an scalable synchronous binary up counter illustrating the use of the generate statement to produce
www.eeworm.com/read/323754/13323112
vhd sdcard_spi.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sdcard_spi is
generic(
write_block_length:integer:=512;
max_block_length:integer:=512;
sd_card_size:i
www.eeworm.com/read/323754/13323375
vhd sdcard_spi.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sdcard_spi is
generic(
write_block_length:integer:=512;
max_block_length:integer:=512;
sd_card_size:i
www.eeworm.com/read/323749/13323453
vhd singt.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity singt is
port(clk:in std_logic;
dout:out std_logic_vector(7 downto 0));
end;
architecture dacc of sin
www.eeworm.com/read/238769/13326456
m uwb_sv_params.m
function [Lam,lambda,Gam,gamma,std_ln_1,std_ln_2,nlos,std_shdw] = uwb_sv_params( cm_num )
% Return S-V model parameters for standard UWB channel models
% Lam Cluster arrival rate (clusters per ns
www.eeworm.com/read/137361/13326664
vhd andarith.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ANDARITH IS -- 选通与门模块
PORT ( ABIN : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOU
www.eeworm.com/read/137360/13326699
vhd tennis.vhd
library ieee;
use ieee.std_logic_1164.all;
entity TENNIS is
port(bain,bbin,clr,clk,souclk:in std_logic;
ballout:out std_logic_vector(7 downto 0);
countah,countal,countbh,countbl:out std_logic_v
www.eeworm.com/read/137359/13326703
vhd top.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TOP IS -- 顶层设计
PORT ( P1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
P3 : OUT STD_LOGIC_VEC