📄 top.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TOP IS -- 顶层设计
PORT ( P1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
P3 : OUT STD_LOGIC_VECTOR(7 DOWNTO 2);
CLK12MHZ,HORL1 : IN STD_LOGIC;
INDEX1 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
CODE1 : OUT INTEGER RANGE 0 TO 15;
HIGH1 : OUT STD_LOGIC;
NUME1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
SPKOUT : OUT STD_LOGIC );
END;
ARCHITECTURE one OF TOP IS
COMPONENT Tone
PORT ( Index : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
CODE : OUT INTEGER RANGE 0 TO 15;
HIGH : OUT STD_LOGIC;
HORL : IN STD_LOGIC;
NUME : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
Tone : OUT INTEGER RANGE 0 TO 16#7FF# ); --11位2进制数
END COMPONENT;
COMPONENT Speaker
PORT ( clk1 : IN STD_LOGIC;
Tone1 : IN INTEGER RANGE 0 TO 16#7FF#; --11位2进制数
SpkS : OUT STD_LOGIC );
END COMPONENT;
SIGNAL Tone2 : INTEGER RANGE 0 TO 16#7FF#;
BEGIN -- 安装U1, U2
P1<= "11100101" ;
P3<= "111111";
u1 : Tone PORT MAP (Index=>Index1, Tone=>Tone2,CODE=>CODE1,
HIGH=>HIGH1,HORL=>HORL1,NUME=>NUME1);
u2 : Speaker PORT MAP (clk1=>CLK12MHZ,Tone1=>Tone2, SpkS=>SPKOUT );
END;
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