buff8.vhd

八位双向三态控制

library ieee;
use ieee.std_logic_1164.all;

entity buff8 is
port(a,b : inout  std_logic_vector(7 downto 0);
     ncs,rd,wr  : in std_logic);
end buff8;

architecture buff8_arch of buff8 is
signal aout ,bout : std_logic_vector(7 downto 0);
begin
process(a,b,ncs,rd,wr)
variable en : std_logic_vector(2 downto 0);
begin
en := ncs & rd & wr;
if en = "001" then bout <= a;
elsif en = "010" then aout <= b;
else aout <= "ZZZZZZZZ";
     bout <= "ZZZZZZZZ";
end if;
b <= bout;
a <= aout;
end process;
end buff8_arch;