计数器：generate语句的应用.txt

VHDL语言应用实例,计数器的设计,用GENERATE语句实现

-- Generated Binary Up Counter
-- The first design entity is a T-type flip-flop. 
-- The second is an scalable synchronous binary up counter illustrating the use of the generate statement to produce regular structures of components. 
-- dowload from: www.fpga.com.cn & www.pld.com.cn


library ieee;
use ieee.std_logic_1164.all;

entity tff is
   port(clk, t, clear : in std_logic; q : buffer std_logic);
end tff;

architecture v1 of tff is
begin
   process(clear, clk)
   begin
      if clear = '1' then
         q <= '0';
      elsif rising_edge(clk) then
         if t = '1' then
            q <= not q;
         else
            null;
         end if;
      end if;      
   end process;
end v1;



library ieee;
use ieee.std_logic_1164.all;

entity bigcntr is
   generic(size : positive := 32);
   port(clk, clear : in std_logic;
         q : buffer std_logic_vector((size-1) downto 0));
end bigcntr;

architecture v1 of bigcntr is

   component tff is
      port(clk, t, clear : in std_logic; q : buffer std_logic);
   end component;

   signal tin : std_logic_vector((size-1) downto 0);

begin

   genttf : for i in (size-1) downto 0 generate
      ttype : tff port map (clk, tin(i), clear, q(i));
   end generate;

   genand : for i in 0 to (size-1) generate
      t0 : if i = 0 generate
         tin(i) <= '1';
      end generate;
      t1_size : if i > 0 generate
         tin(i) <= q(i-1) and tin(i-1);
      end generate;
   end generate;

end v1;