代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/243249/12952758
vhd controller.vhd
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:15:53 09/17/2007
-- Design Name:
-- Module Name: controller
www.eeworm.com/read/243249/12952768
vhd mips.vhd
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:37:58 09/17/2007
-- Design Name:
-- Module Name: MIPS - Beh
www.eeworm.com/read/329087/12980504
vhd gelei.vhd
library ieee;
use ieee.std_logic_1164.all;
entity gelei is
port (c1,c2,c3: in std_logic;
y1,y2,y3:out std_logic);
end gelei;
architecture example2 of gelei is
signal s: std_logic_vector(2
www.eeworm.com/read/328956/12992935
vhd reg1.vhd
--REG1.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG1 IS
PORT(D: IN STD_LOGIC_VECTOR(9 DOWNTO 0);
CLK: IN STD_LOGIC;
Q: OUT STD_LOGIC_VECTOR(9 DOWNTO 0));
END ENTITY
www.eeworm.com/read/328956/12992947
vhd reg2.vhd
--REG2.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG2 IS
PORT(D: IN STD_LOGIC_VECTOR(8 DOWNTO 0);
CLK: IN STD_LOGIC;
Q: OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
END ENTITY
www.eeworm.com/read/242401/13007884
vhd sdr_sdram.vhd
--#######################################################################
--
-- LOGIC CORE: SDR SDRAM Controller
-- MODULE NAME: sdr_sdram()
-- COMPANY: Alte
www.eeworm.com/read/328146/13044797
vhd uarttest.vhd
--============================================================================--
-- Design units : TestBench for miniUART device.
--
-- File name : UARTTest.vhd
--
-- Purpose : Implemen
www.eeworm.com/read/140872/13055386
vhd bchanle.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bchanle is
port(bchclk,clr_b:in std_logic;
badress:out std_logic_vector(8 downto 0));
end bchanle;
archit
www.eeworm.com/read/140872/13056018
vhd achanle.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity achanle is
port(sysclk,clr_a:in std_logic;
aadress:out std_logic_vector(8 downto 0));
end achanle;
archit
www.eeworm.com/read/140872/13056069
vhd phader.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity phader is
port(sysclk:in std_logic;
a:in std_logic_vector(7 downto 0);