mips.vhd

MIPS处理器VHDL代码

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:37:58 09/17/2007 
-- Design Name: 
-- Module Name:    MIPS - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE; 
use IEEE.STD_LOGIC_1164.all;

entity mips is  
    generic(width:   integer := 8;
            regbits: integer := 3);
				
    port(clk,reset:         in  STD_LOGIC;
         memdata:           in  STD_LOGIC_VECTOR(width-1 downto 0);
         memread,memwrite:  out STD_LOGIC;
	      adr,writedata:     out STD_LOGIC_VECTOR(width-1 downto 0));
end;

architecture struct of mips is
    component controller 
        port(
		  clk:            in STD_LOGIC;
	     op:   		  	   in STD_LOGIC_VECTOR(5 downto 0);
	     zero:		  	   in STD_LOGIC;
	     memread, memwrite, alusrca, memtoreg,iord, pcen, regwrite,regdst: out STD_LOGIC;
	     pcsource, alusrcb, aluop:    out STD_LOGIC_VECTOR(1 downto 0);
 	     irwrite:			             out STD_LOGIC_VECTOR(3 downto 0));
    end component;
	 
    component alucontrol
	 port(aluop  :	in  STD_LOGIC_VECTOR(1 downto 0);
	      funct  :	in  STD_LOGIC_VECTOR(5 downto 0);	
	      alucont: out STD_LOGIC_VECTOR(2 downto 0));
    end component;
	 
    component datapath generic(width, regbits: integer);
	 port(clk, reset:	in  STD_LOGIC;
	      memdata:		in  STD_LOGIC_VECTOR(width-1 downto 0);
	      alusrca, memtoreg, iord, pcen,
	      regwrite, regdst:  in  STD_LOGIC;
	      pcsource, alusrcb: in  STD_LOGIC_VECTOR(1 downto 0);
	      irwrite:		       in  STD_LOGIC_VECTOR(3 downto 0);
	      alucont:		       in  STD_LOGIC_VECTOR(2 downto 0);
	      zero: 		       out STD_LOGIC;
	      instr:		       out STD_LOGIC_VECTOR(31 downto 0);
	      adr, writedata:    out STD_LOGIC_VECTOR(width-1 downto 0));
    end component;
	 
    signal instr: STD_LOGIC_VECTOR(31 downto 0);
    signal zero, alusrca, memtoreg, iord, pcen, regwrite, regdst: STD_LOGIC;
    signal aluop, pcsource, alusrcb: STD_LOGIC_VECTOR(1 downto 0);
    signal irwrite: STD_LOGIC_VECTOR(3 downto 0);
    signal alucont: STD_LOGIC_VECTOR(2 downto 0);
begin
    cont: controller port map(reset, instr(31 downto 26), zero,
			                     memread, memwrite, alusrca, memtoreg,
			                     iord, pcen, regwrite, regdst,
			                     pcsource, alusrcb, aluop, irwrite);
										
    ac: alucontrol   port map(aluop,instr(5 downto 0),alucont);
	 
    dp: datapath  generic map(width, regbits)
		               port map(clk, reset, memdata, alusrca,memtoreg,
		                        iord, pcen, regwrite, regdst,
		                        pcsource, alusrcb, irwrite,
		                        alucont, zero, instr, adr, writedata);
end;