gelei.vhd

来自「8选1数据选择器」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all;
entity gelei is
port (c1,c2,c3: in std_logic;
      y1,y2,y3:out std_logic);
end gelei;
architecture example2 of gelei is
signal s: std_logic_vector(2 downto 0);
 begin 
    s<=c1&c2&c3;
    process(c1,c2,c3,y1,y2,y3)
    begin
      case s is
        when "000"=>(y1<=c1,y2<=c1,y3<=c1);
        when "001"=>(y1<="0",y2<="0",y3<="0");
        when "010"=>(y1<="0",y2<="0",y3<="0");
        when "011"=>(y1<="0",y2<="0",y3<="0");
        when "100"=>(y1<="0",y2<="0",y3<="0");
        when "101"=>(y1<="0",y2<="0",y3<="0");
        when "110"=>(y1<="0",y2<="0",y3<="0");
        when "111"=>(y1<="0",y2<="0",y3<="0");
     end case;
   end process;
end example2;