controller.vhd

MIPS处理器VHDL代码

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:15:53 09/17/2007 
-- Design Name: 
-- Module Name:    controller - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE; 
use IEEE.STD_LOGIC_1164.all;

entity controller is  --FSM Controller
    port(clk,reset:      in STD_LOGIC;
         op:			    in STD_LOGIC_VECTOR(5 downto 0);
	      zero:			    in STD_LOGIC;
	      memread, memwrite, alusrca, memtoreg,iord, pcen, regwrite, regdst: out STD_LOGIC;
	      pcsource, alusrcb, aluop:     out STD_LOGIC_VECTOR(1 downto 0);
	      irwrite:		                  out STD_LOGIC_VECTOR(3 downto 0));
end;


architecture synth of controller is 
   type statetype is (FETCH1, FETCH2, FETCH3, FETCH4, DECODE, MEMADR,
			             LBRD, LBWR, SBWR,RTYPEEX, RTYPEWR, BEQEX, JEX);
	constant LB:    STD_LOGIC_VECTOR(5 downto 0) := "100000";
	constant SB:    STD_LOGIC_VECTOR(5 downto 0) := "101000";
	constant RTYPE: STD_LOGIC_VECTOR(5 downto 0) := "000000";
	constant beq:   STD_LOGIC_VECTOR(5 downto 0) := "000100";
	constant J:     STD_LOGIC_VECTOR(5 downto 0) := "000010";
	signal state, nextstate:     statetype;
	signal pcwrite, pcwritecond: STD_LOGIC;
begin
    process (clk) 
	 begin            --state register
	    
	  if reset = '1' then 
			state <= FETCH1;
	   else 
		   if clk'event and clk = '1' then
		    state <= nextstate;
	       end if;
	  end if;
    end process;
	 
   process (state) 
	begin
	irwrite <= "0000";
	pcwrite <= '0'; pcwritecond <= '0';
	regwrite <= '0'; regdst <= '0';
	memread <= '0'; memwrite <= '0';
	alusrca <= '0'; alusrcb <= "00"; aluop <= "00";
	pcsource <= "00";
	iord <= '0'; memtoreg <= '0';
	
	case state is
	    when FETCH1 => memread <= '1';
			             irwrite <= "1000";
			             alusrcb <= "01";
			             pcwrite <= '1';
							 nextstate <=FETCH2;
	    when FETCH2 => memread <= '1';
			             irwrite <= "0100";
			             alusrcb <= "01";
			             pcwrite <= '1'; 
							 nextstate <=FETCH3;
	    when FETCH3 => memread <= '1';
			             irwrite <= "0010";
			             alusrcb <= "01";
			             pcwrite <= '1'; 
							 nextstate <=FETCH4;
	    when FETCH4 => memread <= '1';
			             irwrite <= "0001";
			             alusrcb <= "01";
			             pcwrite <= '1'; 
							 nextstate <=DECODE;
	    when DECODE => alusrcb <= "11";
		                nextstate <=MEMADR;
	    when MEMADR => alusrca <= '1';
			             alusrcb <= "10";
							 nextstate <=LBRD;
	    when LBRD   => memread <= '1';
			             iord <= '1';
							 nextstate <=LBWR;
	    when LBWR   => regwrite <= '1';
			             memtoreg <= '1';
							 nextstate <=SBWR;
	    when SBWR   => memwrite <= '1';
	   		          iord <= '1';
							 nextstate <=RTYPEEX;
	    when RTYPEEX=> alusrca <= '1';
			             aluop <= "10";
							 nextstate <=RTYPEWR;
	    when RTYPEWR=> regdst <= '1';
			             regwrite <= '1';
							 nextstate <=BEQEX;
	    when BEQEX =>  alusrca <= '1';
	   		          aluop <= "01";
			             pcwritecond <= '1';
			             pcsource <= "01";
							 nextstate <=JEX;
	    when JEX   =>  pcwrite <= '1';
			             pcsource <= "10";
							 nextstate <=FETCH1;
	end case;
   end process;
end;