代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
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vhd control_fsm_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
www.eeworm.com/read/331103/12850796
m uwb_sv_params.m
function [Lam,lambda,Gam,gamma,std_ln_1,std_ln_2,nlos,std_shdw] = uwb_sv_params( cm_num )
% Return S-V model parameters for standard UWB channel models
% Lam Cluster arrival rate (clusters per ns
www.eeworm.com/read/330723/12873734
vhd freqdivision.vhd
library ieee;
use ieee.std_logic_1164.all;
entity freqDivision is
port (clk:in std_logic;
scanClk:out std_logic;
systemClk:out std_logic);
end freqDivision;
architecture main of freqDivi
www.eeworm.com/read/330723/12873740
vhd count16.vhd
library ieee;
use ieee.std_logic_1164.all;
entity count16 is
port(clk:in std_logic;
co:out std_logic;
qcnt:buffer std_logic_vector(3 downto 0));
end count16;
architecture main of count16
www.eeworm.com/read/143194/12890102
vhd ir.vhd
-- ir.vhd
-- This module implements the Instruction Register (IR). IR is loaded from
-- memory on the rising edge of "clk" when "IRwrite" is asserted high. It is
-- cleared to zero when "reset" i
www.eeworm.com/read/243676/12926073
vhd cnt10bcd.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cnt10bcd is
Port ( clkin :in std_logic;
co :out std_logic;
qout
www.eeworm.com/read/142712/12929948
m uwb_sv_params.m
function [Lam,lambda,Gam,gamma,std_ln_1,std_ln_2,nlos,std_shdw] = uwb_sv_params( cm_num )
% Return S-V model parameters for standard UWB channel models
% Lam Cluster arrival rate (clusters per ns
www.eeworm.com/read/142672/12931033
mgf 1.mgf
I 000057 55 1828 1131087599660 arch_code_stream
(_unit VHDL (code_stream 0 5 (arch_code_stream 0 13 ))
(_version v28)
(_time 1131087599659 2005.11.04 14:59:59)
(_source (\.\\src\\hw3
www.eeworm.com/read/243601/12931894
vhd serout.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY dctslowout IS
PORT(
clk : IN std_logic ;
doutput : IN std_logic_vector (15 DOWNTO 0) ;
www.eeworm.com/read/142489/12943297
vhd ch9_2_1.vhd
-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--*************************************