📄 count16.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity count16 is
port(clk:in std_logic;
co:out std_logic;
qcnt:buffer std_logic_vector(3 downto 0));
end count16;
architecture main of count16 is
type con is array (0 to 7) of integer range 0 to 3;
constant act:con:=(0,1,0,2,0,1,0,3);
shared variable i:integer range 0 to 7:=0;
signal count:std_logic_vector(3 downto 0):=(others =>'0');
begin
qcnt<=count;
co<='1' when (qcnt="1000") else '0';
process(clk)
begin
if(rising_edge(clk)) then
count(act(i))<=not count(act(i));
if(i=7) then
i:=0;
else i:=i+1;
end if;
end if;
end process;
end main;
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