ch9_2_1.vhd

CH4CH2CH1VHDL 数字电路参考书所有程序9

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY Ch9_2_1 is
	PORT(
		 Din		: IN	STD_LOGIC_VECTOR(7 Downto 0);	-- A/D Data In
		 Dout		: OUT   STD_LOGIC_VECTOR(7 Downto 0);	-- A/D Data Out
		 CP			: IN    STD_LOGIC;		-- CLOCK
		 RST        : IN	STD_LOGIC;		-- System Reset
		 nCS,nWR,nRD: OUT   STD_LOGIC;		-- O/P Signal
		 nINTR		: IN    STD_LOGIC		-- I/P Signal	
		);
END Ch9_2_1;

--*********************************************
ARCHITECTURE a OF Ch9_2_1 IS
	TYPE 	STATE_TYPE IS	(S0,S1,S2,S3);	--State Type Declare
	SIGNAL  State 	: STATE_TYPE;		 	--State Signal Declare
	SIGNAL  EC,nIN	: STD_LOGIC;		--Synchronous Control & A/D nINTR
	SIGNAL  D		: STD_LOGIC_VECTOR(7 Downto 0);	--Read A/D Data
BEGIN

SystemConnection: Block
Begin
	nIn <= nINTR;	
	Dout <= D;				-- A/D Data Out
End Block SystemConnection;

StateChange: Block
Begin
	PROCESS (CP,RST)				
	BEGIN
		IF RST = '1' Then			-- Reset State
				nCS <= '1';
				nWR <= '1';
				nRD <= '1';
				EC <= '0';

				State <= S0;

		ElsIF CP'Event And CP = '1' Then	
			CASE State IS

				WHEN S0 =>			--STATE S0 & Write State
					nCS <= '0';
					nWR <= '0';
					nRD <= '1';
					EC <= '0';

					State <= S1;

				WHEN S1 =>			--STATE S1 & A/D Conversion State
					nCS <= '1';
					nWR <= '1';
					nRD <= '1';
					EC <= '0';
					
					If nIN = '0' Then	--nINTR = '0' ?
						State <= S2;
					End if;

				WHEN S2 =>			--STATE S2 & Read State
					nCS <= '0';
					nWR <= '1';
					nRD <= '0';
					EC <= '1';

					State <= S3;
			
				WHEN S3 =>			--STATE S3
					nCS <= '1';
					nWR <= '1';
					nRD <= '1';
					EC <= '0';

					State <= S0;
					
				WHEN OTHERS =>		--Initial State	
					State <= S0;
					
	 			END CASE;
		ENd If;
	END PROCESS; 
End Block StateChange;


ReadData: Block
Begin
	PROCESS (CP)
	BEGIN 	
		IF CP'Event AND CP = '1' THEN
			IF EC = '1' THEN			-- Read State --> EC = '1'
				D <= Din;		-- Read A/D Convertor Data
			END IF;
		END IF;
	END PROCESS;
End Block ReadData;


END a;