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I 000057 55 1828 1131087599660 arch_code_stream(_unit VHDL (code_stream 0 5 (arch_code_stream 0 13 ))
(_version v28)
(_time 1131087599659 2005.11.04 14:59:59)
(_source (\.\\src\\hw3.vhd\))
(_use (std(standard))(ieee(std_logic_1164)))
(_entity
(_time 1131086727224)
(_use )
)
(_object
(_type (_internal ~std_logic_vector~12 0 6 (_array ~extieee.std_logic_1164.std_logic ((_uto (i 0)(i 2147483647))))))
(_generic (_internal for_detec ~std_logic_vector~12 0 6 (_entity -1 (_string \"11100"\))))
(_port (_internal clk ~extieee.std_logic_1164.std_logic 0 7 (_entity (_in ))))
(_port (_internal reset ~extieee.std_logic_1164.std_logic 0 8 (_entity (_in ))))
(_port (_internal datain ~extieee.std_logic_1164.std_logic 0 9 (_entity (_in ))))
(_port (_internal pmatch ~extieee.std_logic_1164.std_logic 0 10 (_entity (_out ))))
(_type (_internal ~std_logic_vector{4~downto~0}~13 0 14 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 4)(i 0))))))
(_signal (_internal stream ~std_logic_vector{4~downto~0}~13 0 14 (_architecture (_uni ))))
(_signal (_internal i ~extSTD.STANDARD.INTEGER 0 15 (_architecture (_uni ((i 0))))))
(_process
(line__17(_architecture 0 0 17 (_process (_target(3)(4(0))(4(1))(4(2))(4(3))(4(4))(4)(5))(_sensitivity(0)(1))(_read(2)(4)(5)))))
)
(_subprogram
(_external resolved (ieee std_logic_1164 0))
)
(_type (_external ~extieee.std_logic_1164.std_logic (ieee std_logic_1164 std_logic)))
(_type (_external ~extieee.std_logic_1164.std_ulogic (ieee std_logic_1164 std_ulogic)))
(_type (_external ~extieee.std_logic_1164.std_logic_vector (ieee std_logic_1164 std_logic_vector)))
(_type (_external ~extSTD.STANDARD.INTEGER (std STANDARD INTEGER)))
)
(_static
(2 2 2 2 2 )
)
(_model . arch_code_stream 1 -1
)
)
I 000050 55 2161 1131087599670 arch_test(_unit VHDL (test 0 4 (arch_test 0 7 ))
(_version v28)
(_time 1131087599669 2005.11.04 14:59:59)
(_source (\.\\src\\test_stream.vhd\))
(_use (std(standard))(ieee(std_logic_1164)))
(_entity
(_time 1131087098408)
(_use )
)
(_component
(code_stream
(_object
(_generic (_internal for_detec ~std_logic_vector~13 0 10 (_entity -1 (_string \"11100"\))))
(_port (_internal clk ~extieee.std_logic_1164.std_logic 0 11 (_entity (_in ))))
(_port (_internal reset ~extieee.std_logic_1164.std_logic 0 12 (_entity (_in ))))
(_port (_internal datain ~extieee.std_logic_1164.std_logic 0 13 (_entity (_in ))))
(_port (_internal pmatch ~extieee.std_logic_1164.std_logic 0 14 (_entity (_out ))))
)
)
)
(_instantiation U 0 18 (_component code_stream )
(_port
((clk)(clk))
((reset)(reset))
((datain)(datain))
((pmatch)(pmatch))
)
(_use (_entity . code_stream)
)
)
(_object
(_type (_internal ~std_logic_vector~13 0 10 (_array ~extieee.std_logic_1164.std_logic ((_uto (i 0)(i 2147483647))))))
(_signal (_internal clk ~extieee.std_logic_1164.std_logic 0 16 (_architecture (_uni ))))
(_signal (_internal reset ~extieee.std_logic_1164.std_logic 0 16 (_architecture (_uni ))))
(_signal (_internal datain ~extieee.std_logic_1164.std_logic 0 16 (_architecture (_uni ))))
(_signal (_internal pmatch ~extieee.std_logic_1164.std_logic 0 16 (_architecture (_uni ))))
(_process
(clock(_architecture 0 0 20 (_process (_wait_for)(_target(0)))))
(res(_architecture 1 0 28 (_process (_wait_for)(_target(1)))))
(data(_architecture 2 0 36 (_process (_wait_for)(_target(2)))))
)
(_subprogram
(_external resolved (ieee std_logic_1164 0))
)
(_type (_external ~extieee.std_logic_1164.std_logic (ieee std_logic_1164 std_logic)))
(_type (_external ~extieee.std_logic_1164.std_ulogic (ieee std_logic_1164 std_ulogic)))
(_type (_external ~extieee.std_logic_1164.std_logic_vector (ieee std_logic_1164 std_logic_vector)))
)
(_model . arch_test 3 -1
)
)
V 000057 55 1828 1131087601873 arch_code_stream(_unit VHDL (code_stream 0 5 (arch_code_stream 0 13 ))
(_version v28)
(_time 1131087601872 2005.11.04 15:00:01)
(_source (\.\\src\\hw3.vhd\))
(_use (std(standard))(ieee(std_logic_1164)))
(_entity
(_time 1131086727224)
(_use )
)
(_object
(_type (_internal ~std_logic_vector~12 0 6 (_array ~extieee.std_logic_1164.std_logic ((_uto (i 0)(i 2147483647))))))
(_generic (_internal for_detec ~std_logic_vector~12 0 6 (_entity -1 (_string \"11100"\))))
(_port (_internal clk ~extieee.std_logic_1164.std_logic 0 7 (_entity (_in ))))
(_port (_internal reset ~extieee.std_logic_1164.std_logic 0 8 (_entity (_in ))))
(_port (_internal datain ~extieee.std_logic_1164.std_logic 0 9 (_entity (_in ))))
(_port (_internal pmatch ~extieee.std_logic_1164.std_logic 0 10 (_entity (_out ))))
(_type (_internal ~std_logic_vector{4~downto~0}~13 0 14 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 4)(i 0))))))
(_signal (_internal stream ~std_logic_vector{4~downto~0}~13 0 14 (_architecture (_uni ))))
(_signal (_internal i ~extSTD.STANDARD.INTEGER 0 15 (_architecture (_uni ((i 0))))))
(_process
(line__17(_architecture 0 0 17 (_process (_target(4(0))(4(1))(4(2))(4(3))(4(4))(4)(5)(3))(_sensitivity(0)(1))(_read(4)(5)(2)))))
)
(_subprogram
(_external resolved (ieee std_logic_1164 0))
)
(_type (_external ~extieee.std_logic_1164.std_logic (ieee std_logic_1164 std_logic)))
(_type (_external ~extieee.std_logic_1164.std_ulogic (ieee std_logic_1164 std_ulogic)))
(_type (_external ~extieee.std_logic_1164.std_logic_vector (ieee std_logic_1164 std_logic_vector)))
(_type (_external ~extSTD.STANDARD.INTEGER (std STANDARD INTEGER)))
)
(_static
(2 2 2 2 2 )
)
(_model . arch_code_stream 1 -1
)
)
I 000050 55 2161 1131087601913 arch_test(_unit VHDL (test 0 4 (arch_test 0 7 ))
(_version v28)
(_time 1131087601912 2005.11.04 15:00:01)
(_source (\.\\src\\test_stream.vhd\))
(_use (std(standard))(ieee(std_logic_1164)))
(_entity
(_time 1131087098408)
(_use )
)
(_component
(code_stream
(_object
(_generic (_internal for_detec ~std_logic_vector~13 0 10 (_entity -1 (_string \"11100"\))))
(_port (_internal clk ~extieee.std_logic_1164.std_logic 0 11 (_entity (_in ))))
(_port (_internal reset ~extieee.std_logic_1164.std_logic 0 12 (_entity (_in ))))
(_port (_internal datain ~extieee.std_logic_1164.std_logic 0 13 (_entity (_in ))))
(_port (_internal pmatch ~extieee.std_logic_1164.std_logic 0 14 (_entity (_out ))))
)
)
)
(_instantiation U 0 18 (_component code_stream )
(_port
((clk)(clk))
((reset)(reset))
((datain)(datain))
((pmatch)(pmatch))
)
(_use (_entity . code_stream)
)
)
(_object
(_type (_internal ~std_logic_vector~13 0 10 (_array ~extieee.std_logic_1164.std_logic ((_uto (i 0)(i 2147483647))))))
(_signal (_internal clk ~extieee.std_logic_1164.std_logic 0 16 (_architecture (_uni ))))
(_signal (_internal reset ~extieee.std_logic_1164.std_logic 0 16 (_architecture (_uni ))))
(_signal (_internal datain ~extieee.std_logic_1164.std_logic 0 16 (_architecture (_uni ))))
(_signal (_internal pmatch ~extieee.std_logic_1164.std_logic 0 16 (_architecture (_uni ))))
(_process
(clock(_architecture 0 0 20 (_process (_wait_for)(_target(0)))))
(res(_architecture 1 0 28 (_process (_wait_for)(_target(1)))))
(data(_architecture 2 0 36 (_process (_wait_for)(_target(2)))))
)
(_subprogram
(_external resolved (ieee std_logic_1164 0))
)
(_type (_external ~extieee.std_logic_1164.std_logic (ieee std_logic_1164 std_logic)))
(_type (_external ~extieee.std_logic_1164.std_ulogic (ieee std_logic_1164 std_ulogic)))
(_type (_external ~extieee.std_logic_1164.std_logic_vector (ieee std_logic_1164 std_logic_vector)))
)
(_model . arch_test 3 -1
)
)
I 000050 55 2161 1131088136532 arch_test(_unit VHDL (test 0 4 (arch_test 0 7 ))
(_version v28)
(_time 1131088136531 2005.11.04 15:08:56)
(_source (\.\\src\\test_stream.vhd\))
(_use (std(standard))(ieee(std_logic_1164)))
(_entity
(_time 1131087098408)
(_use )
)
(_component
(code_stream
(_object
(_generic (_internal for_detec ~std_logic_vector~13 0 10 (_entity -1 (_string \"11100"\))))
(_port (_internal clk ~extieee.std_logic_1164.std_logic 0 11 (_entity (_in ))))
(_port (_internal reset ~extieee.std_logic_1164.std_logic 0 12 (_entity (_in ))))
(_port (_internal datain ~extieee.std_logic_1164.std_logic 0 13 (_entity (_in ))))
(_port (_internal pmatch ~extieee.std_logic_1164.std_logic 0 14 (_entity (_out ))))
)
)
)
(_instantiation U 0 18 (_component code_stream )
(_port
((clk)(clk))
((reset)(reset))
((datain)(datain))
((pmatch)(pmatch))
)
(_use (_entity . code_stream)
)
)
(_object
(_type (_internal ~std_logic_vector~13 0 10 (_array ~extieee.std_logic_1164.std_logic ((_uto (i 0)(i 2147483647))))))
(_signal (_internal clk ~extieee.std_logic_1164.std_logic 0 16 (_architecture (_uni ))))
(_signal (_internal reset ~extieee.std_logic_1164.std_logic 0 16 (_architecture (_uni ))))
(_signal (_internal datain ~extieee.std_logic_1164.std_logic 0 16 (_architecture (_uni ))))
(_signal (_internal pmatch ~extieee.std_logic_1164.std_logic 0 16 (_architecture (_uni ))))
(_process
(clock(_architecture 0 0 20 (_process (_wait_for)(_target(0)))))
(res(_architecture 1 0 28 (_process (_wait_for)(_target(1)))))
(data(_architecture 2 0 36 (_process (_wait_for)(_target(2)))))
)
(_subprogram
(_external resolved (ieee std_logic_1164 0))
)
(_type (_external ~extieee.std_logic_1164.std_logic (ieee std_logic_1164 std_logic)))
(_type (_external ~extieee.std_logic_1164.std_ulogic (ieee std_logic_1164 std_ulogic)))
(_type (_external ~extieee.std_logic_1164.std_logic_vector (ieee std_logic_1164 std_logic_vector)))
)
(_model . arch_test 3 -1
)
)
I 000027 54 233 0 cfg_test(_configuration VHDL (cfg_test 0 48 (test))
(_version v28)
(_time 1131088136611 2005.11.04 15:08:56)
(_source (\.\\src\\test_stream.vhd\))
(_use (std(standard))(ieee(std_logic_1164)))
(_architecture arch_test
)
)
V 000050 55 2161 1131098615139 arch_test(_unit VHDL (test 0 4 (arch_test 0 7 ))
(_version v28)
(_time 1131098615138 2005.11.04 18:03:35)
(_source (\.\\src\\test_stream.vhd\))
(_use (std(standard))(ieee(std_logic_1164)))
(_entity
(_time 1131087098408)
(_use )
)
(_component
(code_stream
(_object
(_generic (_internal for_detec ~std_logic_vector~13 0 10 (_entity -1 (_string \"11100"\))))
(_port (_internal clk ~extieee.std_logic_1164.std_logic 0 11 (_entity (_in ))))
(_port (_internal reset ~extieee.std_logic_1164.std_logic 0 12 (_entity (_in ))))
(_port (_internal datain ~extieee.std_logic_1164.std_logic 0 13 (_entity (_in ))))
(_port (_internal pmatch ~extieee.std_logic_1164.std_logic 0 14 (_entity (_out ))))
)
)
)
(_instantiation U 0 18 (_component code_stream )
(_port
((clk)(clk))
((reset)(reset))
((datain)(datain))
((pmatch)(pmatch))
)
(_use (_entity . code_stream)
)
)
(_object
(_type (_internal ~std_logic_vector~13 0 10 (_array ~extieee.std_logic_1164.std_logic ((_uto (i 0)(i 2147483647))))))
(_signal (_internal clk ~extieee.std_logic_1164.std_logic 0 16 (_architecture (_uni ))))
(_signal (_internal reset ~extieee.std_logic_1164.std_logic 0 16 (_architecture (_uni ))))
(_signal (_internal datain ~extieee.std_logic_1164.std_logic 0 16 (_architecture (_uni ))))
(_signal (_internal pmatch ~extieee.std_logic_1164.std_logic 0 16 (_architecture (_uni ))))
(_process
(clock(_architecture 0 0 20 (_process (_wait_for)(_target(0)))))
(res(_architecture 1 0 28 (_process (_wait_for)(_target(1)))))
(data(_architecture 2 0 36 (_process (_wait_for)(_target(2)))))
)
(_subprogram
(_external resolved (ieee std_logic_1164 0))
)
(_type (_external ~extieee.std_logic_1164.std_logic (ieee std_logic_1164 std_logic)))
(_type (_external ~extieee.std_logic_1164.std_ulogic (ieee std_logic_1164 std_ulogic)))
(_type (_external ~extieee.std_logic_1164.std_logic_vector (ieee std_logic_1164 std_logic_vector)))
)
(_model . arch_test 3 -1
)
)
V 000027 54 233 0 cfg_test(_configuration VHDL (cfg_test 0 48 (test))
(_version v28)
(_time 1131098615139 2005.11.04 18:03:35)
(_source (\.\\src\\test_stream.vhd\))
(_use (std(standard))(ieee(std_logic_1164)))
(_architecture arch_test
)
)
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