hw3.vhd

来自「设计一个模块」· VHDL 代码 · 共 47 行

library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;

entity code_stream is
generic(for_detec:std_logic_vector:="11100");
port(clk:in std_logic;
	 reset:in std_logic;
	 datain:in std_logic;
	 pmatch:out std_logic);
end code_stream;

architecture arch_code_stream of code_stream is
signal stream:std_logic_vector(4 downto 0);
signal i:integer:=0;
begin
	process(clk,reset)
	begin
		if reset='1' then
			pmatch<='0';
			stream<="00000";
			i<=0;
		elsif clk'event and clk='1' then
			stream(4)<=stream(3); 
			stream(3)<=stream(2);
			stream(2)<=stream(1);
			stream(1)<=stream(0);
			stream(0)<=datain;
			if i<10 then
				i<=i+1;
			end if;			
		end if;
		if  i>4 and stream=for_detec then
			pmatch<='1';
		else
			pmatch<='0';
		end	if;

		
	end process;
	

	
	
	
	
end arch_code_stream;