代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/397324/8055861
vhd balucaideng.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity balucaideng is
port(clk,clr:in std_logic;
l:out std_logic_vecyor(8 downto 1));
end;
architecture
www.eeworm.com/read/397146/8064805
vhd i2c_master_top.vhd
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; top level
www.eeworm.com/read/297001/8066369
vhd function_unit.vhd
library ieee;
use ieee.std_logic_1164.all;
entity function_unit is
port (
FS : in std_logic_vector(3 downto 0);
A, B : in std_logic_vector(15 downto 0);
V : out std_logic;
www.eeworm.com/read/297001/8066425
vhd muxf.vhd
library ieee;
use ieee.std_logic_1164.all;
entity MUXF is
port (
MUXF_0 : in std_logic_vector(15 downto 0);
MUXF_1 : in std_logic_vector(15 downto 0);
MFsel : in std_logic
www.eeworm.com/read/296373/8108679
vhd m1.vhd
--五级m序列发生器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY M1 IS
PORT(reset,CLK: IN STD_LOGIC;
Y: OUT STD_LOGIC);
END ENTITY;
ARCHITECTURE ART OF M1 IS
SIGNAL S1,S2: STD_LOGIC_VE
www.eeworm.com/read/296373/8108682
vhd hdb3.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hdb3 is
port(reset,clk,datain:in std_logic;
dout: out std_logic_vector(1 downto 0));
end;
architectur
www.eeworm.com/read/296345/8109296
txt 交通灯.txt
--1.控制模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY control IS
PORT (clk0,reset0,s0,s1,c0 :IN STD_LOGIC;
ld0 :out std_logic;
www.eeworm.com/read/196140/8112905
txt 1_4.txt
题目：
设计一个1对4分用器（输入：D ，输出： Y3 Y2 Y1 Y0，另有两个输入控制端S1与S0控制输出选择），真值表如图4。
S1 S0 Y3 Y2 Y1 Y0
0 0
0 1
1 0
1 1 D 1 1 0
1 D 1 1
1 1 D 1
1 1 1 D
本软件设计的目的和任务：1.使学
www.eeworm.com/read/296280/8112950
vhd clk.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clk is
port(
clk : in std_logic;
address : out std_logic_vector(5 downto 0));
end clk;
a
www.eeworm.com/read/196115/8114476
vhd abortgenerator.vhd
--****************************************************************************************************
-- Behavioural model of ABORT generation for ARM core simualtion
-- Designed by Ruslan Lepeteno