m1.vhd

来自「hDB3的编解码模块 是在maxplusII 下验证过的 并且下到片子中都正」· VHDL 代码 · 共 25 行

--五级m序列发生器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY M1 IS
 PORT(reset,CLK: IN STD_LOGIC;
      Y: OUT STD_LOGIC);
END ENTITY;

ARCHITECTURE ART OF M1 IS
 SIGNAL S1,S2: STD_LOGIC_VECTOR(4 DOWNTO 0);
 BEGIN
 PROCESS(reset,CLK) IS
 BEGIN
 IF reset='1' THEN S1(0)<='1';
 ELSIF(CLK='1' AND CLK'EVENT) THEN 
   S1<=(S2(0) XOR S2(3))&S2(4 DOWNTO 1);
 END IF;
 S2<=S1;
 Y<=S2(0);
 END PROCESS;
 END;