代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/436000/7779616
vhd symulacja.vhd
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-- Company:
-- Engineer:
--
-- Create Date: 15:00:52 01/26/2009
-- Design Name: led
-- Module Name: C:/D
www.eeworm.com/read/435861/7782617
txt antishakeswitchprocedure.txt
开关防抖程序
library ieee;
use ieee.std_logic_1164.all;
entity dou is
port(din,clk: in std_logic;
dout: out std_logic);
end dou;
architecture beha of dou is
signal x,y:std_logic;
www.eeworm.com/read/435744/7785911
vhd i60bcd.vhd
--The IEEE standard 1164 package, declares std_logic, rising_edge(), etc.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity i60bcd i
www.eeworm.com/read/435744/7785930
vhd regne.vhd
--regne.vhd n-bit register with enable
library ieee ;
use ieee.std_logic_1164.all ;
entity regne is
generic ( n : integer := 12 ) ;
port (
r : in std_logic_vector(n-1 downto 0) ;--register
www.eeworm.com/read/435744/7785983
vhd negative.vhd
--negative.vhd correct negative number circuit
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity negative is
port(
a : in std_logic_vector(11 downto 0);--块
www.eeworm.com/read/435744/7786002
vhd bcdadd.vhd
--bcdadd.vhd 1 digit bcd adder
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcdadd is
port(
a : in std_logic_vector(3 downto 0);--砆
www.eeworm.com/read/435744/7786009
vhd bcd.vhd
--bcd.vhd 1 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd is
port(
a : in std_logic_vector(3 downto 0);--砆
www.eeworm.com/read/435744/7786016
vhd multiplier.vhd
--multiplier.vhd n-bit multiplier
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use work.components.all ;
entity multiplier is
generic ( n : integer := 7; nn :
www.eeworm.com/read/435744/7786032
vhd bcd3.vhd
--bcd3.vhd 3 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd3 is
port(
a : in std_logic_vector(11 downto 0);--砆
www.eeworm.com/read/435661/7788106
txt 4选1数据选择器.txt
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux_4 IS
PORT(e,d0,d1,d2,d3,d5,d6,d7,d8,a,b:IN STD_LOGIC;
q:OUT STD_LOGIC;
)
END ENTITY mux_4;
ARCHITECTU