regne.vhd

来自「包含若干个VHDL小例子」· VHDL 代码 · 共 23 行

--regne.vhd n-bit register with enable
library ieee ;
use ieee.std_logic_1164.all ;

entity regne is
generic ( n : integer := 12 ) ;
port (
  r : in 	std_logic_vector(n-1 downto 0) ;--register input
  e : in 	std_logic ;--enable?1->enable 0->disable
  clock : in 	std_logic ;--clock signal
  q : out std_logic_vector(n-1 downto 0) ) ;--register output
end regne ;
architecture behavior of regne is
begin
  process ( clock )
  begin
    if clock'event and clock = '1' then--clock positive edge trigger
      if e = '1' then
        q <= r ;--data store into register
      end if ;
    end if ;
  end process ;
end behavior ;