代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/440264/7691329
vhd ir.vhd
-- ir.vhd
-- This module implements the Instruction Register (IR). IR is loaded from
-- memory on the rising edge of "clk" when "IRwrite" is asserted high. It is
-- cleared to zero when "reset" i
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vhd pci_io_virtex.vhd
--*****************************************************************************
-- FILE : PCI_IO_Virtex
-- DATE : 1.9.1999
-- REVISION: 1.1
-- DESIGNER: KA
-- Descr : Physical I/O Interfa
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vhd hwtb_ddr1_top.vhd
-------------------------------------------------------------------------------
-- Copyright (c) 2006 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
---
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vhd tennis.vhd
library ieee;
use ieee.std_logic_1164.all;
entity TENNIS is
port(bain,bbin,clr,clk,souclk:in std_logic;
ballout:out std_logic_vector(7 downto 0);
countah,countal,countbh,countbl:out std_logic_v
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vhd cnt8.vhd
LIBRARY IEEE; -- 8进制计数器
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT8 IS
PORT ( CLK : IN STD_LOGIC;
CQ : OU
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vhd cnt5.vhd
LIBRARY IEEE; -- 4进制计数器
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT5 IS
PORT ( CLK : IN STD_LOGIC;
AA : OU
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vhd dec1.vhd
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Dec1 IS
PORT ( CLK : IN STD_LOGIC;
D : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END ;
ARCH
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vhd cnt2.vhd
LIBRARY IEEE; -- 4进制计数器
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT2 IS
PORT ( CLK : IN STD_LOGIC;
CQ : OU
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vhd decd.vhd
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DECD IS
PORT ( CLK : IN STD_LOGIC;
DSPY : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;
D :
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vho cic2_by4_compiler_v1_0.vho
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation